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Hiroshi Kadota - One of the best experts on this subject based on the ideXlab platform.

  • ohmega a vlsi superscalar processor architecture for numerical applications
    International Symposium on Computer Architecture, 1991
    Co-Authors: Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Reiji Segawa, Takeshi Kishida, Yuji Nakai, Hiroshi Kadota
    Abstract:

    multiple instructions per clock cycle, there are at least four This paper describes a VLSI superscalar processor architecture which can sustain very high performance in numericai applications. The architecture performs instructionlevel scheduling statically by the compiler, and performs outof-order issuing and executing of instructions to decrease the stall on the pipelines that dynamically occurs in execution. In this architecture, a pair of instructions are fetched in every clock cycle, decoded simultaneously, and issued to corresponding execution pipelines independently. For ease of instruction-level scheduling by the compiler, the architecture provider: -i) rimultaneoun execution df almost all pairs of instructions including Store-Stare pair and Load-Store pair, ii) simple, low-latency, and easily-paired execution pipeline structure, and iii) high-capacity muiti-ported floating point registers and integer registers. Enhanced performance by the dynamic decrease of the pipeline hazards is achieved by i) efficient data Dependency resolution with novel Directly Tag Compare (DTC) method, ii) non-penalty branch mechanism and simple Control Dependency resolution, and iii) large data transfer ability by the pipelined data cache and 128 bit wide bus bandwidth. An efficient data Dependency resolutioi mechanism, which is realized by using the novel DTC method, synchronized pipeiine operation, and data bypassing network, permits out-of-order instruction issuing and execution. The idea of DTC method is similar to that of dynamic data-flaw architecture with tagged token. The non-penalty branches are realized by three techniques, delayed branch, LOOP instruction that executer counter decrement, compare, and branch in one clock cycle, and non-penalty conditional branch with predicted condition codes. These 'techniques contribute to the decrease of the pipeline stalls occurring at run time. The architecture can achieve 80MFLOPS/80MIPS peak performance at 4OMHz clock and sustain 1.4 to 3.6 times higher performance of simple Multiple Function Unit (MFU) type RISC processors by taking advantage of these techniques.

  • ISCA - OHMEGA : a VLSI superscalar processor architecture for numerical applications
    Proceedings of the 18th annual international symposium on Computer architecture - ISCA '91, 1991
    Co-Authors: Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Reiji Segawa, Takeshi Kishida, Yuji Nakai, Hiroshi Kadota
    Abstract:

    multiple instructions per clock cycle, there are at least four This paper describes a VLSI superscalar processor architecture which can sustain very high performance in numericai applications. The architecture performs instructionlevel scheduling statically by the compiler, and performs outof-order issuing and executing of instructions to decrease the stall on the pipelines that dynamically occurs in execution. In this architecture, a pair of instructions are fetched in every clock cycle, decoded simultaneously, and issued to corresponding execution pipelines independently. For ease of instruction-level scheduling by the compiler, the architecture provider: -i) rimultaneoun execution df almost all pairs of instructions including Store-Stare pair and Load-Store pair, ii) simple, low-latency, and easily-paired execution pipeline structure, and iii) high-capacity muiti-ported floating point registers and integer registers. Enhanced performance by the dynamic decrease of the pipeline hazards is achieved by i) efficient data Dependency resolution with novel Directly Tag Compare (DTC) method, ii) non-penalty branch mechanism and simple Control Dependency resolution, and iii) large data transfer ability by the pipelined data cache and 128 bit wide bus bandwidth. An efficient data Dependency resolutioi mechanism, which is realized by using the novel DTC method, synchronized pipeiine operation, and data bypassing network, permits out-of-order instruction issuing and execution. The idea of DTC method is similar to that of dynamic data-flaw architecture with tagged token. The non-penalty branches are realized by three techniques, delayed branch, LOOP instruction that executer counter decrement, compare, and branch in one clock cycle, and non-penalty conditional branch with predicted condition codes. These 'techniques contribute to the decrease of the pipeline stalls occurring at run time. The architecture can achieve 80MFLOPS/80MIPS peak performance at 4OMHz clock and sustain 1.4 to 3.6 times higher performance of simple Multiple Function Unit (MFU) type RISC processors by taking advantage of these techniques.

Liehuang Zhu - One of the best experts on this subject based on the ideXlab platform.

  • Trust-based workflow refactoring for concurrent scheduling in service-oriented environment
    Concurrency and Computation: Practice and Experience, 2013
    Co-Authors: Mingzhong Wang, Liehuang Zhu, Xuyun Zhang, Lejian Liao
    Abstract:

    SUMMARY Workflow scheduling has been extensively studied to improve the system performance. However, existing approaches are usually built on predefined workflow graph structure, neglecting the possibility that a workflow graph itself may be changeable when certain conditions are satisfied. Therefore, in this paper, we propose the concept of graph refactoring that transforms certain types of sequential tasks to run in parallel without changing system's functionality. We first provide a classification for task dependencies in workflows and identify that previously sequential task ordering in loose Control Dependency can be scheduled to run in parallel as long as supporting services are trustworthy. With this concept, we present a refactoring algorithm to traverse, restructure, and parallelize loose Control dependencies in the graph when the reputations of related executing services are above certain threshold. In addition, refactoring effects on common sub-graph structures are analyzed and discussed. In practice, our algorithm can be integrated into existing workflow management systems as a preprocessor to generate a new functionally equivalent working graph with more concurrent branches for further scheduling. Experiments and analysis show that graph refactoring can improve the system performance scalably because of concurrent execution of previously sequential tasks. Copyright © 2013 John Wiley & Sons, Ltd.

  • CGC - Workflow Refactoring for Concurrent Task Execution
    2012 Second International Conference on Cloud and Green Computing, 2012
    Co-Authors: Mingzhong Wang, Jinjun Chen, Liehuang Zhu
    Abstract:

    The performance and reliability of workflow execution are highly dependent on the scheduling algorithm. However, existing approaches usually confines the scheduling on the predefined workflow structure, neglecting the possibility that a workflow graph itself may be changeable when certain conditions are satisfied. Therefore, in this paper we propose the concept of graph refactoring which transforms certain types of sequential tasks to run in parallel without changing system's functionality. We first propose a classification of task dependencies in DAG-style workflow graphs as data, strict Control, and loose Control Dependency according to task interaction and user requirements, and identify that previously sequential task ordering in loose Control Dependency can be scheduled to run in parallel as long as supporting services are trustworthy. Corresponding refactoring algorithms are designed to traverse, restructure, and parallelize loose Control dependencies in the graph when the reputations of related executing services are above certain threshold. Experiments and analysis show that graph refactoring can improve the system performance scalably because of concurrent execution of previously sequential tasks.

Masaitsu Nakajima - One of the best experts on this subject based on the ideXlab platform.

  • ohmega a vlsi superscalar processor architecture for numerical applications
    International Symposium on Computer Architecture, 1991
    Co-Authors: Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Reiji Segawa, Takeshi Kishida, Yuji Nakai, Hiroshi Kadota
    Abstract:

    multiple instructions per clock cycle, there are at least four This paper describes a VLSI superscalar processor architecture which can sustain very high performance in numericai applications. The architecture performs instructionlevel scheduling statically by the compiler, and performs outof-order issuing and executing of instructions to decrease the stall on the pipelines that dynamically occurs in execution. In this architecture, a pair of instructions are fetched in every clock cycle, decoded simultaneously, and issued to corresponding execution pipelines independently. For ease of instruction-level scheduling by the compiler, the architecture provider: -i) rimultaneoun execution df almost all pairs of instructions including Store-Stare pair and Load-Store pair, ii) simple, low-latency, and easily-paired execution pipeline structure, and iii) high-capacity muiti-ported floating point registers and integer registers. Enhanced performance by the dynamic decrease of the pipeline hazards is achieved by i) efficient data Dependency resolution with novel Directly Tag Compare (DTC) method, ii) non-penalty branch mechanism and simple Control Dependency resolution, and iii) large data transfer ability by the pipelined data cache and 128 bit wide bus bandwidth. An efficient data Dependency resolutioi mechanism, which is realized by using the novel DTC method, synchronized pipeiine operation, and data bypassing network, permits out-of-order instruction issuing and execution. The idea of DTC method is similar to that of dynamic data-flaw architecture with tagged token. The non-penalty branches are realized by three techniques, delayed branch, LOOP instruction that executer counter decrement, compare, and branch in one clock cycle, and non-penalty conditional branch with predicted condition codes. These 'techniques contribute to the decrease of the pipeline stalls occurring at run time. The architecture can achieve 80MFLOPS/80MIPS peak performance at 4OMHz clock and sustain 1.4 to 3.6 times higher performance of simple Multiple Function Unit (MFU) type RISC processors by taking advantage of these techniques.

  • ISCA - OHMEGA : a VLSI superscalar processor architecture for numerical applications
    Proceedings of the 18th annual international symposium on Computer architecture - ISCA '91, 1991
    Co-Authors: Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Reiji Segawa, Takeshi Kishida, Yuji Nakai, Hiroshi Kadota
    Abstract:

    multiple instructions per clock cycle, there are at least four This paper describes a VLSI superscalar processor architecture which can sustain very high performance in numericai applications. The architecture performs instructionlevel scheduling statically by the compiler, and performs outof-order issuing and executing of instructions to decrease the stall on the pipelines that dynamically occurs in execution. In this architecture, a pair of instructions are fetched in every clock cycle, decoded simultaneously, and issued to corresponding execution pipelines independently. For ease of instruction-level scheduling by the compiler, the architecture provider: -i) rimultaneoun execution df almost all pairs of instructions including Store-Stare pair and Load-Store pair, ii) simple, low-latency, and easily-paired execution pipeline structure, and iii) high-capacity muiti-ported floating point registers and integer registers. Enhanced performance by the dynamic decrease of the pipeline hazards is achieved by i) efficient data Dependency resolution with novel Directly Tag Compare (DTC) method, ii) non-penalty branch mechanism and simple Control Dependency resolution, and iii) large data transfer ability by the pipelined data cache and 128 bit wide bus bandwidth. An efficient data Dependency resolutioi mechanism, which is realized by using the novel DTC method, synchronized pipeiine operation, and data bypassing network, permits out-of-order instruction issuing and execution. The idea of DTC method is similar to that of dynamic data-flaw architecture with tagged token. The non-penalty branches are realized by three techniques, delayed branch, LOOP instruction that executer counter decrement, compare, and branch in one clock cycle, and non-penalty conditional branch with predicted condition codes. These 'techniques contribute to the decrease of the pipeline stalls occurring at run time. The architecture can achieve 80MFLOPS/80MIPS peak performance at 4OMHz clock and sustain 1.4 to 3.6 times higher performance of simple Multiple Function Unit (MFU) type RISC processors by taking advantage of these techniques.

Mingzhong Wang - One of the best experts on this subject based on the ideXlab platform.

  • Trust-based workflow refactoring for concurrent scheduling in service-oriented environment
    Concurrency and Computation: Practice and Experience, 2013
    Co-Authors: Mingzhong Wang, Liehuang Zhu, Xuyun Zhang, Lejian Liao
    Abstract:

    SUMMARY Workflow scheduling has been extensively studied to improve the system performance. However, existing approaches are usually built on predefined workflow graph structure, neglecting the possibility that a workflow graph itself may be changeable when certain conditions are satisfied. Therefore, in this paper, we propose the concept of graph refactoring that transforms certain types of sequential tasks to run in parallel without changing system's functionality. We first provide a classification for task dependencies in workflows and identify that previously sequential task ordering in loose Control Dependency can be scheduled to run in parallel as long as supporting services are trustworthy. With this concept, we present a refactoring algorithm to traverse, restructure, and parallelize loose Control dependencies in the graph when the reputations of related executing services are above certain threshold. In addition, refactoring effects on common sub-graph structures are analyzed and discussed. In practice, our algorithm can be integrated into existing workflow management systems as a preprocessor to generate a new functionally equivalent working graph with more concurrent branches for further scheduling. Experiments and analysis show that graph refactoring can improve the system performance scalably because of concurrent execution of previously sequential tasks. Copyright © 2013 John Wiley & Sons, Ltd.

  • CGC - Workflow Refactoring for Concurrent Task Execution
    2012 Second International Conference on Cloud and Green Computing, 2012
    Co-Authors: Mingzhong Wang, Jinjun Chen, Liehuang Zhu
    Abstract:

    The performance and reliability of workflow execution are highly dependent on the scheduling algorithm. However, existing approaches usually confines the scheduling on the predefined workflow structure, neglecting the possibility that a workflow graph itself may be changeable when certain conditions are satisfied. Therefore, in this paper we propose the concept of graph refactoring which transforms certain types of sequential tasks to run in parallel without changing system's functionality. We first propose a classification of task dependencies in DAG-style workflow graphs as data, strict Control, and loose Control Dependency according to task interaction and user requirements, and identify that previously sequential task ordering in loose Control Dependency can be scheduled to run in parallel as long as supporting services are trustworthy. Corresponding refactoring algorithms are designed to traverse, restructure, and parallelize loose Control dependencies in the graph when the reputations of related executing services are above certain threshold. Experiments and analysis show that graph refactoring can improve the system performance scalably because of concurrent execution of previously sequential tasks.

J-l. Philippe - One of the best experts on this subject based on the ideXlab platform.

  • Multi-granularity Metrics For The Era Of Strongly Personalized SOCs
    2003
    Co-Authors: Y. Le Moullec, J-ph. Diguet, Mohamed Abid, Nader Ben Amor, J-l. Philippe
    Abstract:

    This paper details the first step of the Design Trotter framework for design space exploration applied to dedicated SOCs. The aim of this step is to provide metrics in order to guide the designer and the synthesis tool towards an efficient application architecture matching. This work presents a computation of metrics at all levels of the application graph-based hierarchy. These metrics are computed through data and Control Dependency analysis. They quantify the memory, Control and processing orientations as well as the average of parallelism for different granularities.

  • DATE - Multi-Granularity Metrics for the Era of Strongly Personalized SOCs
    2003 Design Automation and Test in Europe Conference and Exhibition, 1
    Co-Authors: Y. Le Moullec, N. Ben Amor, J-ph. Diguet, Mohamed Abid, J-l. Philippe
    Abstract:

    This paper details the first step of the Design Trotter framework for design space exploration applied to dedicated SOCs. The aim of this step is to provide metrics in order to guide the designer and the synthesis tool towards an efficient application architecture matching. This work presents a computation of metrics at all levels of the application graph-based hierarchy. These metrics are computed through data and Control Dependency analysis. They quantify the memory, Control and processing orientations as well as the average of parallelism for different granularities.