The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Rajesh Mehra - One of the best experts on this subject based on the ideXlab platform.
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Frequency Synthesizer for Software Radios
2016Co-Authors: Bindiya Kamboj, Rajesh MehraAbstract:In this paper an efficient approach is presented to design and implement Direct Digital Frequency Synthesizer (DDFS) with high speed and spectral purity for wireless applications like Software Defined Radio (SDR). The implementation is based upon efficient utilization of embedded slices and LUT’s of the target device to enhance the speed of the proposed design. The proposed DDFS is designed & simulated with MATLAB and Xilinx AccelDSP, synthesized with Xilinx Synthesis Tool (XST) and implemented on Spartan 3E & Virtex 2P based XC3S500E and XC2VP307FF896 FPGA target device respectively. The proposed design can operate at an estimated frequency of 116.2 MHz and 146.5 MHz, along with the minimum period of 8.605 ns and 6.8240 ns for the Spartan 3e and Virtex 2 Pro FPGA device, respectively. The FFT analysis of developed DDFS shows enhanced SFDR of 86.17dB
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for Enhanced Resource Utilization
2015Co-Authors: Rajesh Mehra, S S PattnaikAbstract:In this paper a hybrid approach is presented to design and implement a GSM digital down convertor for enhanced resource utilization. The proposed DDC has been implemented by hybridizing the multiplier less and multiplier based decimators. A multiplier less CIC decimator has been used to reduce the cost by reducing the multiplier requirement. Two computationally efficient equiripple polyphase decomposition structure based decimators have been to reduce the filter order and hardware complexity. The embedded multipliers, LUTs and BRAMs have been efficiently utilized to enhance the system performance and resource utilization. The proposed GSM DDC has been designed and simulated Matlab and Simulink, synthesized with Xilinx Synthesis Tool and implemented on Virtex-II Pro based xc2vp20 FPGA device. The proposed design has shown a minimum period of 159.96 MHz with enhance resource utilization ranging from 4-12 % in terms slices, flip flops LUTs, BRAMs and multipliers
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Optimized Design of CIC Decimator using Embedded LUTs of FPGA for Wireless Communication Systems
2015Co-Authors: Rajesh Mehra, Swapna DeviAbstract:Abstract—In this paper an efficient multiplier less technique is presented to design a high speed CIC decimator for wireless applications like SDR and GSM. The implementation is based on efficient utilization of embedded LUTs of target device to enhance the speed of proposed design. It is an efficient method because the use of embedded LUTs not only increases the speed but also saves the resources on the target device. The fully pipelined CIC decimator is designed with Matlab, simulated with Modelsim, synthesized with Xilinx Synthesis Tool (XST), and implemented on Spartan-3E based XC3s500e-4fg320 target device. The proposed design can be operated at an estimated frequency of 206.2 MHz by consuming considerably less available resources of target device to provide cost effective solution for SDR applications. The power consumption of the proposed design is 0.08098W at 27.1°C junction temperature. Keywords—ASIC, CIC, FPGA, GSM, SD
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FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications
2015Co-Authors: Rajesh Mehra, Rashmi AroraAbstract:Abstract — In this paper an efficient multiplier-less technique is presented to design and implement a high speed CIC decimator for wireless applications like SDR and GSM. The Cascaded Integrator Comb is a commonly used decimation filter which performs sample rate conversion (SRC) using only additions/subtractions. The implementation is based on efficient utilization of embedded LUTs of the target device to enhance the speed of proposed design. It is an efficient method used to design and implement CIC decimator because the use of embedded LUTs not only increases the speed but also saves the resources on the target device. The fully pipelined CIC decimator is designed with Matlab, simulated with Xilinx AccelDSP, synthesized with Xilinx Synthesis Tool (XST), and implemented on Virtex-II based XC2VP50-6 target FPGA device. The proposed design can operate at an estimated frequency of 276.6 MHz by consuming considerably less resources on target device to provide cost effective solution for SDR based wireless applications. Keywords- CIC; FPGA; FPGA; GSM; LUT; SDR. I
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FPGA based Speed Efficient Decimator using Distributed Arithmetic Algorithm
2014Co-Authors: Rajesh Mehra, Lajwanti SinghAbstract:In this paper, an efficient FPGA implementation of a multipliers less decimator is presented for wireless application. DA has been used to implement a decimator taking advantage of embedded LUT based structure of FPGAs. Speed and area efficient solution is designed using half band polyphase decomposition FIR structure. The proposed decimator has been designed with MATLAB and synthesized with Xilinx Synthesis Tool (XST)10.1 and implemented on Spartan-3E based 3s500efg.320-4 FPGA device. Improvement of 28 % in speed and 50 % in area has been observed as compared to MAC based approach
Sergio Bampi - One of the best experts on this subject based on the ideXlab platform.
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exploring efficient adder compressors for power efficient sum of squared differences design
International Conference on Electronics Circuits and Systems, 2020Co-Authors: Morgana M A Da Rosa, Guilherme Paim, Leandro M G Rocha, Eduardo Costa, Sergio BampiAbstract:This work explores the 8–2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture. SSD is a distortion metric of the motion estimation in the High-Efficiency Video Coding (HEVC) standard. Distortion metrics are the most time-consuming operations of the encoder. SSD hardware architecture consists of a sum tree that accumulates the calculation of the partial values. The addition tree in the SSD opens an opportunity of exploring efficient addition schemes such as the combinations of efficient adder compressors. The SSD architectures herein presented are compared regarding power dissipation using real video sequences. Our work overcomes the state-of-the-art related work which they investigated different SSD hardware architectures concluding that employing the Synthesis Tool arithmetic operators are the best choice to reduce the power dissipation. According to our results, we reveal that the SSD employing the 8–2 hierarchical adder compressor combined with a Brent-Kung adder in the final sum saves on average 29.4 % of total power dissipation, when comparing with SSD implemented using the arithmetic operators automatically selected by the Synthesis Tool.
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power efficient sum of absolute differences hardware architecture using adder compressors for integer motion estimation design
IEEE Transactions on Circuits and Systems I-regular Papers, 2017Co-Authors: Bianca Silveira, Claudio Machado Diniz, Guilherme Paim, Brunno Abreu, Mateus Grellert, Eduardo Antonio Cesar Da Costa, Sergio BampiAbstract:Sum of absolute differences (SAD) calculation is one of the most time-consuming operations of video encoders compatible with the high efficiency video coding standard. SAD hardware architectures employ an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper exploits different adder compressors structures into the SAD hardware architecture. The architectures were synthesized to 45-nm CMOS standard cells. Synthesis results show that SAD architecture using 8–2 compressor composed with 4–2 compressors and Kogge–Stone adder in the recombination line reduces power dissipation by 25.5% on average when compared with the SAD architecture using conventional adders from a state-of-the-art Synthesis Tool. Our throughput analysis shows that the designed SAD units are capable of encoding full HD ( $1920\times 1080$ ) videos in real time at 30 frames/s.
Tom Melham - One of the best experts on this subject based on the ideXlab platform.
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equivalence checking of a floating point unit against a high level c model
Formal Methods, 2016Co-Authors: Rajdeep Mukherjee, Saurabh Joshi, Andreas Griesmayer, Daniel Kroening, Tom MelhamAbstract:Semiconductor companies have increasingly adopted a methodology that starts with a system-level design specification in C/C++/SystemC. This model is extensively simulated to ensure correct functionality and performance. Later, a Register Transfer Level (RTL) implementation is created in Verilog, either manually by a designer or automatically by a high-level Synthesis Tool. It is essential to check that the C and Verilog programs are consistent. In this paper, we present a two-step approach, embodied in two equivalence checking Tools, VerifOx and hw-cbmc, to validate designs at the software and RTL levels, respectively. VerifOx is used for equivalence checking of an untimed software model in C against a high-level reference model in C. hw-cbmc verifies the equivalence of a Verilog RTL implementation against an untimed software model in C. To evaluate our Tools, we applied them to a commercial floating-point arithmetic unit (FPU) from ARM and an open-source dual-path floating-point adder.
Rolf Findeisen - One of the best experts on this subject based on the ideXlab platform.
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optimized fpga implementation of model predictive control for embedded systems using high level Synthesis Tool
IEEE Transactions on Industrial Informatics, 2018Co-Authors: Sergio Lucia, D Navarro, Oscar Lucia, Pablo Zometa, Rolf FindeisenAbstract:Model predictive control (MPC) is an optimization-based strategy for high-performance control that is attracting increasing interest. While MPC requires the online solution of an optimization problem, its ability to handle multivariable systems and constraints makes it a very powerful control strategy specially for MPC of embedded systems, which have an ever increasing amount of sensing and computation capabilities. We argue that the implementation of MPC on field programmable gate arrays (FPGAs) using automatic Tools is nowadays possible, achieving cost-effective successful applications on fast or resource-constrained systems. The main burden for the implementation of MPC on FPGAs is the challenging design of the necessary algorithms. We outline an approach to achieve a software-supported optimized implementation of MPC on FPGAs using high-level Synthesis Tools and automatic code generation. The proposed strategy exploits the arithmetic operations necessaries to solve optimization problems to tailor an FPGA design, which allows a tradeoff between energy, memory requirements, cost, and achievable speed. We show the capabilities and the simplicity of use of the proposed methodology on two different examples and illustrate its advantages over a microcontroller implementation.
H Boumeridja - One of the best experts on this subject based on the ideXlab platform.
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digital implementation of artificial neural networks from vhdl description to fpga implementation
International Work-Conference on Artificial and Natural Neural Networks, 1999Co-Authors: Nouma Izeboudjen, Ahcene Farah, Sabrina Titri, H BoumeridjaAbstract:This paper deals with a top down design methodology of an artificial neural network (ANN) based upon parametric VHDL description of the network. To come off early in the design process a high regular architecture was achieved. Then, the VHDL parametric description of the network was realized. The description has the advantage of being generic, flexible and can be easily changed at the user demand. To validate our approach, an ANN for electrocardiogram (ECG) arrhythmia's classification is passed through a Synthesis Tool, GALILEO, for FPGA implementation.
