The Experts below are selected from a list of 12663 Experts worldwide ranked by ideXlab platform
Ingrid Verbauwhede - One of the best experts on this subject based on the ideXlab platform.
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aes based security Coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security Coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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an interactive codesign environment for domain specific Coprocessors
ACM Transactions on Design Automation of Electronic Systems, 2006Co-Authors: Patrick Schaumont, Doris Ching, Ingrid VerbauwhedeAbstract:Energy-efficient embedded systems rely on domain-specific Coprocessors for dedicated tasks such as baseband processing, video coding, or encryption. We present a language and design environment called GEZEL that can be used for the design, verification and implementation of such Coprocessor-based systems.The GEZEL environment creates a platform simulator by combining a hardware simulation kernel with one or more instruction-set simulators. The hardware part of the platform is programmed in GEZEL, a deterministic, cycle-true and implementation-oriented hardware description language. GEZEL designs are scripted, allowing the hardware configuration of the platform simulator to be changed quickly without going through lengthy recompiles. For this reason, we call the environment interactive. We present the execution ladder as an optimization framework to balance interactivity against simulation speed.We demonstrate our approach using several designs including an AES encryption Coprocessor and a Viterbi decoding Coprocessor. We discuss the advantages of our approach as opposed to more conventional approaches using SystemC and Verilog/VHDL.
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aes based cryptographic and biometric security Coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security Coprocessor that consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical Coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first Coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second Coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The Coprocessor is part of a security-partitioned embedded system called ThumbPod.
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a side channel leakage free Coprocessor ic in 0 18 spl mu m cmos for embedded aes based cryptographic and biometric processing
Design Automation Conference, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC and its design techniques. The IC has been fabricated in 0.18/spl mu/m CMOS. The Coprocessor, which is used for embedded cryptographic and biometric processing, consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint-matching oracle, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first, 'secure', Coprocessor is implemented using a logic style called wave dynamic digital logic (WDDL) and a layout technique called differential routing. The second, 'insecure', Coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure Coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure Coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.
Nikolay Panchenko - One of the best experts on this subject based on the ideXlab platform.
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Effective SIMD vectorization for intel Xeon Phi Coprocessors
Scientific Programming, 2015Co-Authors: Xinmin Tian, Serguei V. Preis, Sergey S. Kozhukhov, Matt Masten, Aleksei G. Cherkasov, Hideki Saito, Eric Garcia, Nikolay PanchenkoAbstract:Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel Xeon Phi Coprocessors. In this paper, we present several effective SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel MIC specific alignment optimization, and small matrix transpose/multiplication 2D vectorization implemented in the IntelC/C++ and Fortran production compilers for Intel Xeon Phi Coprocessors. A set of workloads from several application domains is employed to conduct the performance study of our SIMD vectorization techniques. The performance results show that we achieved up to 12.5x performance gain on the Intel Xeon Phi Coprocessor. We also demonstrate a 2000x performance speedup from the seamless integration of SIMD vectorization and parallelization.
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Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors
2013 IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum, 2013Co-Authors: Xinmin Tian, Serguei V. Preis, Eric N. Garcia, Sergey S. Kozhukhov, Matt Masten, Aleksei G. Cherkasov, Hideki Saito, Nikolay PanchenkoAbstract:Intel® Xeon Phi Coprocessor is based on the Intel® Many Integrated Core (Intel® MIC) architecture, which is an innovative new processor architecture that combines abundant thread parallelism with long SIMD vector units. Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel® Xeon Phi Coprocessors. In this paper, we present several practical SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel® MIC specific alignment optimization, and small matrix transpose/multiplication 2-D vectorization implemented in the Intel® C/C++ and Fortran production compilers for Intel® Xeon Phi Coprocessors. A set of workloads from several application domains is employed to conduct the performance study of our SIMD vectorization techniques. The performance results show that we achieved up to 12.5x performance gain on the Intel® Xeon Phi Coprocessor.
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IPDPS Workshops - Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors
2013 IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum, 2013Co-Authors: Xinmin Tian, Serguei V. Preis, Sergey S. Kozhukhov, Matt Masten, Aleksei G. Cherkasov, Hideki Saito, Eric Garcia, Nikolay PanchenkoAbstract:Intel® Xeon Phi Coprocessor is based on the Intel® Many Integrated Core (Intel® MIC) architecture, which is an innovative new processor architecture that combines abundant thread parallelism with long SIMD vector units. Efficiently exploiting SIMD vector units is one of the most important aspects in achieving high performance of the application code running on Intel® Xeon Phi Coprocessors. In this paper, we present several practical SIMD vectorization techniques such as less-than-full-vector loop vectorization, Intel® MIC specific alignment optimization, and small matrix transpose/multiplication 2-D vectorization implemented in the Intel® C/C++ and Fortran production compilers for Intel® Xeon Phi Coprocessors. A set of workloads from several application domains is employed to conduct the performance study of our SIMD vectorization techniques. The performance results show that we achieved up to 12.5x performance gain on the Intel® Xeon Phi Coprocessor.
Kris Tiri - One of the best experts on this subject based on the ideXlab platform.
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aes based security Coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security Coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based cryptographic and biometric security Coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security Coprocessor that consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical Coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first Coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second Coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The Coprocessor is part of a security-partitioned embedded system called ThumbPod.
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a side channel leakage free Coprocessor ic in 0 18 spl mu m cmos for embedded aes based cryptographic and biometric processing
Design Automation Conference, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC and its design techniques. The IC has been fabricated in 0.18/spl mu/m CMOS. The Coprocessor, which is used for embedded cryptographic and biometric processing, consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint-matching oracle, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first, 'secure', Coprocessor is implemented using a logic style called wave dynamic digital logic (WDDL) and a layout technique called differential routing. The second, 'insecure', Coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure Coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure Coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.
Patrick Schaumont - One of the best experts on this subject based on the ideXlab platform.
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aes based security Coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security Coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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an interactive codesign environment for domain specific Coprocessors
ACM Transactions on Design Automation of Electronic Systems, 2006Co-Authors: Patrick Schaumont, Doris Ching, Ingrid VerbauwhedeAbstract:Energy-efficient embedded systems rely on domain-specific Coprocessors for dedicated tasks such as baseband processing, video coding, or encryption. We present a language and design environment called GEZEL that can be used for the design, verification and implementation of such Coprocessor-based systems.The GEZEL environment creates a platform simulator by combining a hardware simulation kernel with one or more instruction-set simulators. The hardware part of the platform is programmed in GEZEL, a deterministic, cycle-true and implementation-oriented hardware description language. GEZEL designs are scripted, allowing the hardware configuration of the platform simulator to be changed quickly without going through lengthy recompiles. For this reason, we call the environment interactive. We present the execution ladder as an optimization framework to balance interactivity against simulation speed.We demonstrate our approach using several designs including an AES encryption Coprocessor and a Viterbi decoding Coprocessor. We discuss the advantages of our approach as opposed to more conventional approaches using SystemC and Verilog/VHDL.
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aes based cryptographic and biometric security Coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security Coprocessor that consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical Coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first Coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second Coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The Coprocessor is part of a security-partitioned embedded system called ThumbPod.
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a side channel leakage free Coprocessor ic in 0 18 spl mu m cmos for embedded aes based cryptographic and biometric processing
Design Automation Conference, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC and its design techniques. The IC has been fabricated in 0.18/spl mu/m CMOS. The Coprocessor, which is used for embedded cryptographic and biometric processing, consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint-matching oracle, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first, 'secure', Coprocessor is implemented using a logic style called wave dynamic digital logic (WDDL) and a layout technique called differential routing. The second, 'insecure', Coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure Coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure Coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.
D D Hwang - One of the best experts on this subject based on the ideXlab platform.
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aes based security Coprocessor ic in 0 18 muhbox m cmos with resistance to differential power analysis side channel attacks
IEEE Journal of Solid-state Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18- $muhbox m$ CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based security Coprocessor ic in 0 18 μm cmos with resistance to differential power analysis side channel attacks
Symposium on VLSI Circuits, 2006Co-Authors: D D Hwang, Kris Tiri, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC fabricated in 0.18-μm CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first Coprocessor was implemented using standard cells and regular routing techniques. The second Coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure Coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure Coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.
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aes based cryptographic and biometric security Coprocessor ic in 0 18 spl mu m cmos resistant to side channel power analysis attacks
Symposium on VLSI Circuits, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:This paper describes an embedded security Coprocessor that consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint matching oracle, template storage, and an interface unit. Two functionally-identical Coprocessors are fabricated using a TSMC 6M 0.18-/spl mu/m process. The first Coprocessor uses standard cells and encrypts at 3.84 Gb/s. The second Coprocessor uses wave dynamic differential logic (WDDL) combined with differential routing to combat side-channel information leakage through power analysis attacks. It encrypts at 0.99 Gb/s. The Coprocessor is part of a security-partitioned embedded system called ThumbPod.
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a side channel leakage free Coprocessor ic in 0 18 spl mu m cmos for embedded aes based cryptographic and biometric processing
Design Automation Conference, 2005Co-Authors: Kris Tiri, D D Hwang, A Hodjat, Bocheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid VerbauwhedeAbstract:Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant Coprocessor IC and its design techniques. The IC has been fabricated in 0.18/spl mu/m CMOS. The Coprocessor, which is used for embedded cryptographic and biometric processing, consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint-matching oracle, template storage, and an interface unit. Two functionally identical Coprocessors have been fabricated on the same die. The first, 'secure', Coprocessor is implemented using a logic style called wave dynamic digital logic (WDDL) and a layout technique called differential routing. The second, 'insecure', Coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure Coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure Coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.