The Experts below are selected from a list of 52689 Experts worldwide ranked by ideXlab platform
John Sartori - One of the best experts on this subject based on the ideXlab platform.
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recovery driven design exploiting error resilience in design of energy efficient processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional computer-aided design (CAD) methodologies optimize a processor module for Correct Operation and prohibit timing violations during nominal Operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of Correct Operation. The target ER is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal Operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target ER. We show how this design-level methodology can be extended to design recovery-driven processors-processors that are optimized to take advantage of hardware or software error resilience. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of ERs to create soft processors-processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of ERs. We demonstrate significant power benefits over conventional design-11.8% on average over all modules and ER targets, and up to 29.1% for individual modules. Processor-level benefits were 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases.
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recovery driven design a power minimization methodology for error tolerant processor modules
Design Automation Conference, 2010Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional CAD methodologies optimize a processor module for Correct Operation, and prohibit timing violations during nominal Operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of Correct Operation. We show that significant power benefits are possible from a recovery-driven design flow that deliberately allows errors caused by voltage overscaling ([10],[3]) to occur during nominal Operation, while relying on an error recovery technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target error rate. We demonstrate power benefits of up to 25%, 19%, 22%, 24%, 20%, 28%, and 20% versus traditional P&R at error rates of 0.125%, 0.25%, 0.5%, 1%, 2%, 4%, and 8%, respectively. Coupling recovery-driven design with an error recovery technique enables increased efficiency and additional power savings.
Andrew B. Kahng - One of the best experts on this subject based on the ideXlab platform.
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recovery driven design exploiting error resilience in design of energy efficient processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional computer-aided design (CAD) methodologies optimize a processor module for Correct Operation and prohibit timing violations during nominal Operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of Correct Operation. The target ER is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal Operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target ER. We show how this design-level methodology can be extended to design recovery-driven processors-processors that are optimized to take advantage of hardware or software error resilience. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of ERs to create soft processors-processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of ERs. We demonstrate significant power benefits over conventional design-11.8% on average over all modules and ER targets, and up to 29.1% for individual modules. Processor-level benefits were 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases.
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recovery driven design a power minimization methodology for error tolerant processor modules
Design Automation Conference, 2010Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional CAD methodologies optimize a processor module for Correct Operation, and prohibit timing violations during nominal Operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of Correct Operation. We show that significant power benefits are possible from a recovery-driven design flow that deliberately allows errors caused by voltage overscaling ([10],[3]) to occur during nominal Operation, while relying on an error recovery technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target error rate. We demonstrate power benefits of up to 25%, 19%, 22%, 24%, 20%, 28%, and 20% versus traditional P&R at error rates of 0.125%, 0.25%, 0.5%, 1%, 2%, 4%, and 8%, respectively. Coupling recovery-driven design with an error recovery technique enables increased efficiency and additional power savings.
Agnieszka świderskamocek - One of the best experts on this subject based on the ideXlab platform.
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ionic liquids as electrolytes for li ion batteries an overview of electrochemical studies
Journal of Power Sources, 2009Co-Authors: Andrzej Lewandowski, Agnieszka świderskamocekAbstract:Abstract The paper reviews properties of room temperature ionic liquids (RTILs) as electrolytes for lithium and lithium-ion batteries. It has been shown that the formation of the solid electrolyte interface (SEI) on the anode surface is critical to the Correct Operation of secondary lithium-ion batteries, including those working with ionic liquids as electrolytes. The SEI layer may be formed by electrochemical transformation of (i) a molecular additive, (ii) RTIL cations or (iii) RTIL anions. Such properties of RTIL electrolytes as viscosity, conductivity, vapour pressure and lithium-ion transport numbers are also discussed from the point of view of their influence on battery performance.
Seokhyeong Kang - One of the best experts on this subject based on the ideXlab platform.
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recovery driven design exploiting error resilience in design of energy efficient processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional computer-aided design (CAD) methodologies optimize a processor module for Correct Operation and prohibit timing violations during nominal Operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of Correct Operation. The target ER is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal Operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target ER. We show how this design-level methodology can be extended to design recovery-driven processors-processors that are optimized to take advantage of hardware or software error resilience. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of ERs to create soft processors-processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of ERs. We demonstrate significant power benefits over conventional design-11.8% on average over all modules and ER targets, and up to 29.1% for individual modules. Processor-level benefits were 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases.
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recovery driven design a power minimization methodology for error tolerant processor modules
Design Automation Conference, 2010Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional CAD methodologies optimize a processor module for Correct Operation, and prohibit timing violations during nominal Operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of Correct Operation. We show that significant power benefits are possible from a recovery-driven design flow that deliberately allows errors caused by voltage overscaling ([10],[3]) to occur during nominal Operation, while relying on an error recovery technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target error rate. We demonstrate power benefits of up to 25%, 19%, 22%, 24%, 20%, 28%, and 20% versus traditional P&R at error rates of 0.125%, 0.25%, 0.5%, 1%, 2%, 4%, and 8%, respectively. Coupling recovery-driven design with an error recovery technique enables increased efficiency and additional power savings.
Rakesh Kumar - One of the best experts on this subject based on the ideXlab platform.
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recovery driven design exploiting error resilience in design of energy efficient processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional computer-aided design (CAD) methodologies optimize a processor module for Correct Operation and prohibit timing violations during nominal Operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of Correct Operation. The target ER is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal Operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target ER. We show how this design-level methodology can be extended to design recovery-driven processors-processors that are optimized to take advantage of hardware or software error resilience. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of ERs to create soft processors-processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of ERs. We demonstrate significant power benefits over conventional design-11.8% on average over all modules and ER targets, and up to 29.1% for individual modules. Processor-level benefits were 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases.
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recovery driven design a power minimization methodology for error tolerant processor modules
Design Automation Conference, 2010Co-Authors: Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John SartoriAbstract:Conventional CAD methodologies optimize a processor module for Correct Operation, and prohibit timing violations during nominal Operation. In this paper, we propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of Correct Operation. We show that significant power benefits are possible from a recovery-driven design flow that deliberately allows errors caused by voltage overscaling ([10],[3]) to occur during nominal Operation, while relying on an error recovery technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target error rate. We demonstrate power benefits of up to 25%, 19%, 22%, 24%, 20%, 28%, and 20% versus traditional P&R at error rates of 0.125%, 0.25%, 0.5%, 1%, 2%, 4%, and 8%, respectively. Coupling recovery-driven design with an error recovery technique enables increased efficiency and additional power savings.
