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The Experts below are selected from a list of 72 Experts worldwide ranked by ideXlab platform

Taylor R. Efland - One of the best experts on this subject based on the ideXlab platform.

  • high voltage drain extended mos transistors for 0 18 spl mu m logic cmos process
    IEEE Transactions on Electron Devices, 2001
    Co-Authors: Jozef C. Mitros, Hisashi Shichijo, Alec J. Morton, D. Goodpaster, Chinyu Tsai, M Kunz, D Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology. These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages BV/sub dss/>10 V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of I/sub ds/(V/sub ds/,V/sub gs/), I/sub gs/(V/sub ds/), and BV(L) plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

  • High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process
    30th European Solid-State Device Research Conference, 2000
    Co-Authors: Jozef C. Mitros, C.-y. Tsai, Hisashi Shichijo, Keith E. Kunz, Alec J. Morton, D. Goodpaster, Dan M. Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

Jozef C. Mitros - One of the best experts on this subject based on the ideXlab platform.

  • high voltage drain extended mos transistors for 0 18 spl mu m logic cmos process
    IEEE Transactions on Electron Devices, 2001
    Co-Authors: Jozef C. Mitros, Hisashi Shichijo, Alec J. Morton, D. Goodpaster, Chinyu Tsai, M Kunz, D Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology. These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages BV/sub dss/>10 V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of I/sub ds/(V/sub ds/,V/sub gs/), I/sub gs/(V/sub ds/), and BV(L) plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

  • High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process
    30th European Solid-State Device Research Conference, 2000
    Co-Authors: Jozef C. Mitros, C.-y. Tsai, Hisashi Shichijo, Keith E. Kunz, Alec J. Morton, D. Goodpaster, Dan M. Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

Karen Shrier - One of the best experts on this subject based on the ideXlab platform.

  • Polymer Based Interposer offering Si Matched CTE + ESD Protection
    2013
    Co-Authors: Karen Shrier
    Abstract:

    For 2.5 D package integration interposers based on silicon have widely been investigated. However, their high Cost Adder to the package is a major drawback. An alternative interposer based on polymer- nanoparticle compound material is introduced. It can be manufactured in large volume by low Cost processes. Depending on polymer layer structure a CTE varying between 0 to 8 ppm/ °C can be adjusted. A polymer system which has a CTE close to Si of 2.6 ppm/ °C is used for a thermally matched interposer. The material is less fragile than silicon or glass. Copper vias through the polymer substrate have been manufactured with a diameter of 2 um by laser drill. The manufactured thickness of the interposer varies between 200 um and as low as 85 um. In addition, by choice of appropriate nano particles the interposer can act as overvoltage protection element where regions between wires become conductive under high voltage conditions. This enables an intrinsic ESD protection implemented into the interposer protecting ...

  • Polymer Based Interposer offering Si Matched CTE + ESD Protection
    Additional Conferences (Device Packaging HiTEC HiTEN and CICMT), 2013
    Co-Authors: Karen Shrier
    Abstract:

    For 2.5 D package integration interposers based on silicon have widely been investigated. However, their high Cost Adder to the package is a major drawback. An alternative interposer based on polymer- nanoparticle compound material is introduced. It can be manufactured in large volume by low Cost processes. Depending on polymer layer structure a CTE varying between 0 to 8 ppm/ °C can be adjusted. A polymer system which has a CTE close to Si of 2.6 ppm/ °C is used for a thermally matched interposer. The material is less fragile than silicon or glass. Copper vias through the polymer substrate have been manufactured with a diameter of 2 um by laser drill. The manufactured thickness of the interposer varies between 200 um and as low as 85 um. In addition, by choice of appropriate nano particles the interposer can act as overvoltage protection element where regions between wires become conductive under high voltage conditions. This enables an intrinsic ESD protection implemented into the interposer protecting the stacked dies against ESD discharges as high as 15 kV IEC.

Hisashi Shichijo - One of the best experts on this subject based on the ideXlab platform.

  • high voltage drain extended mos transistors for 0 18 spl mu m logic cmos process
    IEEE Transactions on Electron Devices, 2001
    Co-Authors: Jozef C. Mitros, Hisashi Shichijo, Alec J. Morton, D. Goodpaster, Chinyu Tsai, M Kunz, D Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology. These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages BV/sub dss/>10 V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of I/sub ds/(V/sub ds/,V/sub gs/), I/sub gs/(V/sub ds/), and BV(L) plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

  • High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process
    30th European Solid-State Device Research Conference, 2000
    Co-Authors: Jozef C. Mitros, C.-y. Tsai, Hisashi Shichijo, Keith E. Kunz, Alec J. Morton, D. Goodpaster, Dan M. Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

Alec J. Morton - One of the best experts on this subject based on the ideXlab platform.

  • high voltage drain extended mos transistors for 0 18 spl mu m logic cmos process
    IEEE Transactions on Electron Devices, 2001
    Co-Authors: Jozef C. Mitros, Hisashi Shichijo, Alec J. Morton, D. Goodpaster, Chinyu Tsai, M Kunz, D Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology. These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages BV/sub dss/>10 V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of I/sub ds/(V/sub ds/,V/sub gs/), I/sub gs/(V/sub ds/), and BV(L) plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

  • High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process
    30th European Solid-State Device Research Conference, 2000
    Co-Authors: Jozef C. Mitros, C.-y. Tsai, Hisashi Shichijo, Keith E. Kunz, Alec J. Morton, D. Goodpaster, Dan M. Mosher, Taylor R. Efland
    Abstract:

    Complementary high-voltage drain extended (DE) MOS transistors were implemented into Texas Instruments' state-of-the-art production advanced analog and digital 1.5-1.8 V CMOS technology (1), (2). These transistors allow for 5-V drain operating voltage using the core gate oxide and have drain breakdown voltages V. Experimental results along with Suprem4 and MEDICI simulation results are presented to explain their operation. The novel p-channel transistors use an isolated compensated p-well as a drain extension. The n-channel version uses n-well as a drain extension. Experimental test results of , , and plots demonstrate DE-MOS performance. The work was focused on performance optimization with zero process modification and hence no Cost Adder.

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