The Experts below are selected from a list of 243 Experts worldwide ranked by ideXlab platform
Akihiro Wakahara - One of the best experts on this subject based on the ideXlab platform.
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operation of monolithically integrated digital Circuits with light emitting diodes fabricated in lattice matched si iii v n si heterostructure
Applied Physics Express, 2010Co-Authors: Keisuke Yamane, Kenta Noguchi, Seizo Tanaka, Yuzo Furukawa, Hiroshi Okada, Hiroo Yonezu, Akihiro WakaharaAbstract:This report presents the successful operation of a 1-bit Counter Circuit with an optical output as a demonstration of monolithic optoelectronic integrated Circuits. The Circuit was fabricated in a lattice-matched Si/III–V–N/Si heterostructure, using p-type metal oxide semiconductor field effect transistors and light emitting diodes (LEDs). The generation of structural defects was significantly suppressed and smooth surfaces were formed. The carrier concentration of the Si-capping layer was decreased to (0.8–1.2)×1017 cm-3 by increasing the growth temperature. In the resulting chips, the red light emission from the LEDs was in synchronization with the logical values of input and output voltages.
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Monolithically-Integrated Digital Circuits with Light Emitting Diodes in Lattice-Matched Si/III-V-N/Si Heterostructure
2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010Co-Authors: Akihiro Wakahara, Keisuke Yamane, Kenta Noguchi, Seizo Tanaka, Yuzo Furukawa, Hiroshi Okada, Hiroo YonezuAbstract:Monolithic integration of a one-bit Counter Circuit with a light-emitting diode as an optical output was fabricated in a structural defect-free Si/III-V-N/Si heterostructure. The generation of structural defects was well suppressed by the simultaneous use of an initial thin GaP intermediate layer and the III-V-N active layer lattice-matched to Si. The origin of relatively high residual carrier concentration was attributed to the accumulated P atoms in the Si growth chamber from sample holder. The carrier concentration of 0.8-1.2×1017cm-3 was achieved by increasing the Si-growth temperature. The one-bit Counter OEIC composed of p-type metal oxide semiconductor field effect transistors (p-MOSFETs) and light-emitting diodes (LEDs) was fabricated in Si-capping layer and the embedded III-V-N layer, respectively. This one-bit Counter Circuit output one pulse every two input pulses, indicating its normal operation. The red light emission from the LEDs synchronized with the logical values of input and output voltages. These results imply that Si-based digital Circuits and III-V-N based LEDs can be monolithically integrated in a single chip.
A.g. Toth - One of the best experts on this subject based on the ideXlab platform.
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A 60-GHz NbN single-flux quantum Counter Circuit
IEEE Journal of Solid-State Circuits, 1991Co-Authors: J.w. Spargo, J.e. Cooper, G.e. Kerber, G.r. King, R.s. Morris, A.g. TothAbstract:A Josephson binary Counter using single-flux quanta transitions of DC SQUIDs (superconducting quantum interference devices) has been fabricated using an eight-level NbN-based process. High-speed binary division has been demonstrated at 4.2 K, with single-cell counting observed at 60 GHz using the Josephson voltage-to-frequency relationship. Count rate was primarily limited by conservative process and design rules. The Counter was designed for operation at 4.2 K. At 8-10 K, the beta /sub L/ of the SQUIDs would not allow operation, though the junction characteristics were good.
Ugur Cilingiroglu - One of the best experts on this subject based on the ideXlab platform.
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A compact high-speed (31,5) parallel Counter Circuit based on capacitive threshold-logic gates
IEEE Journal of Solid-State Circuits, 1996Co-Authors: Yusuf Leblebici, H. Ozdemir, A. Kepkep, Ugur CilingirogluAbstract:A novel high-speed Circuit implementation of the (31,5)-parallel Counter (i.e., population Counter) based on capacitive threshold logic (CTL) is presented. The Circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel Counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic Circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the Circuit can be operated in synchronous as well as in asynchronous mode. The Counter Circuit is implemented using conventional 1.2 /spl mu/m double-poly CMOS technology, and it occupies a silicon area of about 0.08 mm/sup 2/. Extensive post-layout simulations indicate that the Circuit has a typical input-to-output propagation delay of less than 3 ns, and the test Circuit is shown to operate reliably when consecutive 31-b input vectors are applied at a rate of up to 16 Mvectors/s. With its demonstrated data processing capability of about 500 Mb/s, the CTL-based (31,5) parallel Counter offers a number of application possibilities, e.g., in high-speed parallel multiplier arrays and data encoding Circuits.
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A Compact Parallel (31,5)-Counter Circuit Based on Capacitive Threshold-Logic Gates
1995Co-Authors: Yusuf Leblebici, H. Ozdemir, A. Kepkep, Ugur CilingirogluAbstract:A novel high-speed Circuit implementation of the (31,5)-Counter (i.e., the 31-bit data compressor) based on capacitive threshold logic (CTL) is presented. The Circuit consists of 20 threshold logic gates arranged in two stages. The charge-based CTL gates are essentially dynamic Circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the Circuit can be operated in synchronous as well as in asynchronous mode. The compressor Circuit is implemented using conventional 1.2 ?m double-poly CMOS technology, and it occupies a silicon area of (583 × 297) ?m2. Experimental results indicate that the test Circuit has a maximum input-to-output propagation delay of 40 ns, and it is shown to operate reliably when consecutive 31-bit input vectors are applied at a rate of up to 16 Mvectors/s, which corresponds to a data processing capability of about 500 Mbits/s.
Chunliang Lin - One of the best experts on this subject based on the ideXlab platform.
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synthesizing genetic sequential logic Circuit with clock pulse generator
BMC Systems Biology, 2014Co-Authors: Chia Hua Chuang, Chunliang LinAbstract:Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic Circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping Circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic Counter Circuit based on the topology of the digital sequential logic Circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic Circuits which plays a key role in the sequential logic Circuit with specific operational frequency. A cascaded genetic logic Circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic Circuits, genetic sequential logic Circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.
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Synthesizing genetic sequential logic Circuit with clock pulse generator
BMC Systems Biology, 2014Co-Authors: Chia Hua Chuang, Chunliang LinAbstract:Background Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results This paper presents a genetic sequential logic Circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping Circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic Counter Circuit based on the topology of the digital sequential logic Circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic Circuits which plays a key role in the sequential logic Circuit with specific operational frequency. Conclusions A cascaded genetic logic Circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic Circuits, genetic sequential logic Circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.
Keisuke Yamane - One of the best experts on this subject based on the ideXlab platform.
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operation of monolithically integrated digital Circuits with light emitting diodes fabricated in lattice matched si iii v n si heterostructure
Applied Physics Express, 2010Co-Authors: Keisuke Yamane, Kenta Noguchi, Seizo Tanaka, Yuzo Furukawa, Hiroshi Okada, Hiroo Yonezu, Akihiro WakaharaAbstract:This report presents the successful operation of a 1-bit Counter Circuit with an optical output as a demonstration of monolithic optoelectronic integrated Circuits. The Circuit was fabricated in a lattice-matched Si/III–V–N/Si heterostructure, using p-type metal oxide semiconductor field effect transistors and light emitting diodes (LEDs). The generation of structural defects was significantly suppressed and smooth surfaces were formed. The carrier concentration of the Si-capping layer was decreased to (0.8–1.2)×1017 cm-3 by increasing the growth temperature. In the resulting chips, the red light emission from the LEDs was in synchronization with the logical values of input and output voltages.
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Monolithically-Integrated Digital Circuits with Light Emitting Diodes in Lattice-Matched Si/III-V-N/Si Heterostructure
2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2010Co-Authors: Akihiro Wakahara, Keisuke Yamane, Kenta Noguchi, Seizo Tanaka, Yuzo Furukawa, Hiroshi Okada, Hiroo YonezuAbstract:Monolithic integration of a one-bit Counter Circuit with a light-emitting diode as an optical output was fabricated in a structural defect-free Si/III-V-N/Si heterostructure. The generation of structural defects was well suppressed by the simultaneous use of an initial thin GaP intermediate layer and the III-V-N active layer lattice-matched to Si. The origin of relatively high residual carrier concentration was attributed to the accumulated P atoms in the Si growth chamber from sample holder. The carrier concentration of 0.8-1.2×1017cm-3 was achieved by increasing the Si-growth temperature. The one-bit Counter OEIC composed of p-type metal oxide semiconductor field effect transistors (p-MOSFETs) and light-emitting diodes (LEDs) was fabricated in Si-capping layer and the embedded III-V-N layer, respectively. This one-bit Counter Circuit output one pulse every two input pulses, indicating its normal operation. The red light emission from the LEDs synchronized with the logical values of input and output voltages. These results imply that Si-based digital Circuits and III-V-N based LEDs can be monolithically integrated in a single chip.
