The Experts below are selected from a list of 8097 Experts worldwide ranked by ideXlab platform
Tomohiko Takagi - One of the best experts on this subject based on the ideXlab platform.
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state transition tuple Coverage Criterion for extended place transition net based testing
Pacific Rim International Symposium on Dependable Computing, 2019Co-Authors: Tomohiko Takagi, Ryo Kurozumi, Tetsuro KatayamaAbstract:This paper shows a STT (State Transition Tuple) Coverage Criterion for extended place/transition net-based testing. A STT as a measuring object consists of state transitions whose execution may trigger a target failure. The test efficiency is evaluated based on the ratio of STTs executed by test cases.
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PRDC - State Transition Tuple Coverage Criterion for Extended Place/Transition Net-Based Testing
2019 IEEE 24th Pacific Rim International Symposium on Dependable Computing (PRDC), 2019Co-Authors: Tomohiko Takagi, Ryo Kurozumi, Tetsuro KatayamaAbstract:This paper shows a STT (State Transition Tuple) Coverage Criterion for extended place/transition net-based testing. A STT as a measuring object consists of state transitions whose execution may trigger a target failure. The test efficiency is evaluated based on the ratio of STTs executed by test cases.
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the pushdown automaton and its Coverage Criterion for testing undo redo functions of software
Annual ACIS International Conference on Computer and Information Science, 2010Co-Authors: Tomohiko Takagi, Zengo FurukawaAbstract:UR (undo/redo) functions of software play a great role as the achievement of usability, and they are widely used. However, there are no systematic methods of testing the UR functions that are essentially complex. This paper shows systematic method of modeling the behavior of software using a PDA (pushdown automaton) and generating testcases for the UR functions. The testcase generation is based on the Coverage Criterion designed for the PDA. We applied this method to an example of software and evaluated its effectiveness.
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concurrent n switch Coverage Criterion for generating test cases from place transition nets
Annual ACIS International Conference on Computer and Information Science, 2010Co-Authors: Tomohiko Takagi, Naoya Oyaizu, Zengo FurukawaAbstract:A PN (place/transition net) is known as an algebraic model that is useful for describing concurrent, distributed and asynchronous properties of software, and it is also recognized as a model of MBT (model-based testing) that is an important technique for developing high quality software. We propose a concurrent N-switch Coverage Criterion to generate test cases of high Coverage levels from a PN representing test specifications of software. All sequences of successive fireable transitions of length N+1 on the PN can be covered by executing test cases that satisfy the concurrent N-switch Coverage Criterion. This paper shows its processes, work products, algorithms, and examples.
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ACIS-ICIS - Concurrent N-Switch Coverage Criterion for Generating Test Cases from Place/Transition Nets
2010 IEEE ACIS 9th International Conference on Computer and Information Science, 2010Co-Authors: Tomohiko Takagi, Naoya Oyaizu, Zengo FurukawaAbstract:A PN (place/transition net) is known as an algebraic model that is useful for describing concurrent, distributed and asynchronous properties of software, and it is also recognized as a model of MBT (model-based testing) that is an important technique for developing high quality software. We propose a concurrent N-switch Coverage Criterion to generate test cases of high Coverage levels from a PN representing test specifications of software. All sequences of successive fireable transitions of length N+1 on the PN can be covered by executing test cases that satisfy the concurrent N-switch Coverage Criterion. This paper shows its processes, work products, algorithms, and examples.
Tetsuro Katayama - One of the best experts on this subject based on the ideXlab platform.
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state transition tuple Coverage Criterion for extended place transition net based testing
Pacific Rim International Symposium on Dependable Computing, 2019Co-Authors: Tomohiko Takagi, Ryo Kurozumi, Tetsuro KatayamaAbstract:This paper shows a STT (State Transition Tuple) Coverage Criterion for extended place/transition net-based testing. A STT as a measuring object consists of state transitions whose execution may trigger a target failure. The test efficiency is evaluated based on the ratio of STTs executed by test cases.
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PRDC - State Transition Tuple Coverage Criterion for Extended Place/Transition Net-Based Testing
2019 IEEE 24th Pacific Rim International Symposium on Dependable Computing (PRDC), 2019Co-Authors: Tomohiko Takagi, Ryo Kurozumi, Tetsuro KatayamaAbstract:This paper shows a STT (State Transition Tuple) Coverage Criterion for extended place/transition net-based testing. A STT as a measuring object consists of state transitions whose execution may trigger a target failure. The test efficiency is evaluated based on the ratio of STTs executed by test cases.
Huarui Lin - One of the best experts on this subject based on the ideXlab platform.
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map Coverage a novel Coverage Criterion for testing thread safe classes
Automated Software Engineering, 2019Co-Authors: Zan Wang, Yingquan Zhao, Shuang Liu, Jun Sun, Xiang Chen, Huarui LinAbstract:Concurrent programs must be thoroughly tested, as concurrency bugs are notoriously hard to detect. Code Coverage criteria can be used to quantify the richness of a test suite (e.g., whether a program has been tested sufficiently) or provide practical guidelines on test case generation (e.g., as objective functions used in program fuzzing engines). Traditional code Coverage criteria are, however, designed for sequential programs and thus ineffective for concurrent programs. In this work, we introduce a novel code Coverage Criterion for testing thread-safe classes called MAP-Coverage (short for memory-access patterns). The motivation is that concurrency bugs are often correlated with certain memory-access patterns, and thus it is desirable to comprehensively cover all memory-access patterns. Furthermore, we propose a testing method for maximizing MAP-Coverage. Our method has been implemented as a self-contained toolkit, and the experimental results on 20 benchmark programs show that our toolkit outperforms existing testing methods. Lastly, we show empirically that there exists positive correlation between MAP-Coverage and the effectiveness of a set of test executions.
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ASE - MAP-Coverage: a novel Coverage Criterion for testing thread-safe classes
2019 34th IEEE ACM International Conference on Automated Software Engineering (ASE), 2019Co-Authors: Zan Wang, Yingquan Zhao, Shuang Liu, Jun Sun, Xiang Chen, Huarui LinAbstract:Concurrent programs must be thoroughly tested, as concurrency bugs are notoriously hard to detect. Code Coverage criteria can be used to quantify the richness of a test suite (e.g., whether a program has been tested sufficiently) or provide practical guidelines on test case generation (e.g., as objective functions used in program fuzzing engines). Traditional code Coverage criteria are, however, designed for sequential programs and thus ineffective for concurrent programs. In this work, we introduce a novel code Coverage Criterion for testing thread-safe classes called MAP-Coverage (short for memory-access patterns). The motivation is that concurrency bugs are often correlated with certain memory-access patterns, and thus it is desirable to comprehensively cover all memory-access patterns. Furthermore, we propose a testing method for maximizing MAP-Coverage. Our method has been implemented as a self-contained toolkit, and the experimental results on 20 benchmark programs show that our toolkit outperforms existing testing methods. Lastly, we show empirically that there exists positive correlation between MAP-Coverage and the effectiveness of a set of test executions.
Zan Wang - One of the best experts on this subject based on the ideXlab platform.
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map Coverage a novel Coverage Criterion for testing thread safe classes
Automated Software Engineering, 2019Co-Authors: Zan Wang, Yingquan Zhao, Shuang Liu, Jun Sun, Xiang Chen, Huarui LinAbstract:Concurrent programs must be thoroughly tested, as concurrency bugs are notoriously hard to detect. Code Coverage criteria can be used to quantify the richness of a test suite (e.g., whether a program has been tested sufficiently) or provide practical guidelines on test case generation (e.g., as objective functions used in program fuzzing engines). Traditional code Coverage criteria are, however, designed for sequential programs and thus ineffective for concurrent programs. In this work, we introduce a novel code Coverage Criterion for testing thread-safe classes called MAP-Coverage (short for memory-access patterns). The motivation is that concurrency bugs are often correlated with certain memory-access patterns, and thus it is desirable to comprehensively cover all memory-access patterns. Furthermore, we propose a testing method for maximizing MAP-Coverage. Our method has been implemented as a self-contained toolkit, and the experimental results on 20 benchmark programs show that our toolkit outperforms existing testing methods. Lastly, we show empirically that there exists positive correlation between MAP-Coverage and the effectiveness of a set of test executions.
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ASE - MAP-Coverage: a novel Coverage Criterion for testing thread-safe classes
2019 34th IEEE ACM International Conference on Automated Software Engineering (ASE), 2019Co-Authors: Zan Wang, Yingquan Zhao, Shuang Liu, Jun Sun, Xiang Chen, Huarui LinAbstract:Concurrent programs must be thoroughly tested, as concurrency bugs are notoriously hard to detect. Code Coverage criteria can be used to quantify the richness of a test suite (e.g., whether a program has been tested sufficiently) or provide practical guidelines on test case generation (e.g., as objective functions used in program fuzzing engines). Traditional code Coverage criteria are, however, designed for sequential programs and thus ineffective for concurrent programs. In this work, we introduce a novel code Coverage Criterion for testing thread-safe classes called MAP-Coverage (short for memory-access patterns). The motivation is that concurrency bugs are often correlated with certain memory-access patterns, and thus it is desirable to comprehensively cover all memory-access patterns. Furthermore, we propose a testing method for maximizing MAP-Coverage. Our method has been implemented as a self-contained toolkit, and the experimental results on 20 benchmark programs show that our toolkit outperforms existing testing methods. Lastly, we show empirically that there exists positive correlation between MAP-Coverage and the effectiveness of a set of test executions.
Xiang Chen - One of the best experts on this subject based on the ideXlab platform.
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map Coverage a novel Coverage Criterion for testing thread safe classes
Automated Software Engineering, 2019Co-Authors: Zan Wang, Yingquan Zhao, Shuang Liu, Jun Sun, Xiang Chen, Huarui LinAbstract:Concurrent programs must be thoroughly tested, as concurrency bugs are notoriously hard to detect. Code Coverage criteria can be used to quantify the richness of a test suite (e.g., whether a program has been tested sufficiently) or provide practical guidelines on test case generation (e.g., as objective functions used in program fuzzing engines). Traditional code Coverage criteria are, however, designed for sequential programs and thus ineffective for concurrent programs. In this work, we introduce a novel code Coverage Criterion for testing thread-safe classes called MAP-Coverage (short for memory-access patterns). The motivation is that concurrency bugs are often correlated with certain memory-access patterns, and thus it is desirable to comprehensively cover all memory-access patterns. Furthermore, we propose a testing method for maximizing MAP-Coverage. Our method has been implemented as a self-contained toolkit, and the experimental results on 20 benchmark programs show that our toolkit outperforms existing testing methods. Lastly, we show empirically that there exists positive correlation between MAP-Coverage and the effectiveness of a set of test executions.
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ASE - MAP-Coverage: a novel Coverage Criterion for testing thread-safe classes
2019 34th IEEE ACM International Conference on Automated Software Engineering (ASE), 2019Co-Authors: Zan Wang, Yingquan Zhao, Shuang Liu, Jun Sun, Xiang Chen, Huarui LinAbstract:Concurrent programs must be thoroughly tested, as concurrency bugs are notoriously hard to detect. Code Coverage criteria can be used to quantify the richness of a test suite (e.g., whether a program has been tested sufficiently) or provide practical guidelines on test case generation (e.g., as objective functions used in program fuzzing engines). Traditional code Coverage criteria are, however, designed for sequential programs and thus ineffective for concurrent programs. In this work, we introduce a novel code Coverage Criterion for testing thread-safe classes called MAP-Coverage (short for memory-access patterns). The motivation is that concurrency bugs are often correlated with certain memory-access patterns, and thus it is desirable to comprehensively cover all memory-access patterns. Furthermore, we propose a testing method for maximizing MAP-Coverage. Our method has been implemented as a self-contained toolkit, and the experimental results on 20 benchmark programs show that our toolkit outperforms existing testing methods. Lastly, we show empirically that there exists positive correlation between MAP-Coverage and the effectiveness of a set of test executions.
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SAC - A test suite reduction approach based on pairwise interaction of requirements
Proceedings of the 2011 ACM Symposium on Applied Computing - SAC '11, 2011Co-Authors: Xiang Chen, Lijiu Zhang, Haigang Zhao, Ziyuan Wang, Xiaobing Sun, Daoxu ChenAbstract:Test suite reduction is one of the effective techniques to reduce the cost of regression testing. In particular, it tries to identify and remove redundant test cases according to a specific test Coverage Criterion. However, the excessive reduction in test cases may also significantly weaken the fault detection ability of the original test suite. In this paper, we conjecture that covering interaction of test requirements can improve the fault detection ability and propose a new test suite reduction approach. As a preliminary study, we firstly propose a pairwise interaction based Coverage Criterion (PWIC). Then we propose a pairwise interaction of requirements based test suite reduction approach (PWIR). To assess the feasibility and usefulness of our proposed approach, we implement PWIR approach and conduct an empirical study on seven real C programs. After analyzing the results of the empirical studies, we conclude that our approach can improve the fault detection ability without severely increasing the reduced test suite size.
