The Experts below are selected from a list of 177 Experts worldwide ranked by ideXlab platform
Hiroaki Kikuchi - One of the best experts on this subject based on the ideXlab platform.
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Cryptographic Operation Load-Balancing between Cryptographic Module and CPU
2015 IEEE 29th International Conference on Advanced Information Networking and Applications, 2015Co-Authors: Yohei Kaneko, Takamichi Saito, Hiroaki KikuchiAbstract:Mobile devices such as smartphones and tables have permeated into our daily lives and are now often indispensable because of the constant Internet access they provide. Furthermore, with ever increasing concerns regarding privacy and security, it has become popular to utilize Cryptographic Operations when accessing Web application servers from such devices. However, since such Operations cause high loading on the central processing units (CPUs) of personal computers (PCs) or servers, mobile device CPUs now often come equipped with hardware Cryptographic modules. These Cryptographic modules are frequently utilized by many mobile device applications via a process known as offloading. However, when all Cryptographic Operations can be offloaded to Cryptographic modules, device CPUs may become idle, which is an ineffective use of total computing resources. In this paper, we propose the simultaneous balanced offloading of Cryptographic Operations to the Cryptographic module of an AM3358 processor and CPU via load-balancing and then evaluate the performance of our implementation. We evaluated our proposed system and concluded that while it is capable of working effectively, in most cases files smaller than approximately 1000 bytes can be executed faster via the CPU alone, whereas when files are larger than 1000 bytes, the proposed system is faster. In the case of encrypting or decrypting a 7 Kbyte file, our proposed system is twice as fast as 'CPU only' Operation.
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AINA - Cryptographic Operation Load-Balancing between Cryptographic Module and CPU
2015 IEEE 29th International Conference on Advanced Information Networking and Applications, 2015Co-Authors: Yohei Kaneko, Takamichi Saito, Hiroaki KikuchiAbstract:Mobile devices such as smartphones and tables have permeated into our daily lives and are now often indispensable because of the constant Internet access they provide. Furthermore, with ever increasing concerns regarding privacy and security, it has become popular to utilize Cryptographic Operations when accessing Web application servers from such devices. However, since such Operations cause high loading on the central processing units (CPUs) of personal computers (PCs) or servers, mobile device CPUs now often come equipped with hardware Cryptographic modules. These Cryptographic modules are frequently utilized by many mobile device applications via a process known as offloading. However, when all Cryptographic Operations can be offloaded to Cryptographic modules, device CPUs may become idle, which is an ineffective use of total computing resources. In this paper, we propose the simultaneous balanced offloading of Cryptographic Operations to the Cryptographic module of an AM3358 processor and CPU via load-balancing and then evaluate the performance of our implementation. We evaluated our proposed system and concluded that while it is capable of working effectively, in most cases files smaller than approximately 1000 bytes can be executed faster via the CPU alone, whereas when files are larger than 1000 bytes, the proposed system is faster. In the case of encrypting or decrypting a 7 Kbyte file, our proposed system is twice as fast as 'CPU only' Operation.
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Cryptanalysis of Modification to Self-Certified Group-Oriented Cryptosystem Without A Combiner
International Journal of Network Security, 2007Co-Authors: Willy Susilo, Hiroaki KikuchiAbstract:In a (t, n) group-oriented cryptosystem collaboration of at least t participants is required to perform a designated Cryptographic Operation. This type of Cryptographic Operation is very important to support an ad-hoc type network, such as the one that is built using Bluetooth or ad-hoc wireless LAN, since the existence of a combiner is not required to decrypt an encrypted message. In the earlier paper, it was shown that a group-oriented encryption scheme, as proposed by Saeednia and Ghodosi, can be subjected to a conspiracy attack in which two participants collude to decrypt an encrypted message. Recently, it was shown that the modified scheme is subjected to a conspiracy attack of at least three group members with probability 0.608. In this paper, we show a stronger result that shows any conspiracy of at least three group members can collude and decrypt an encrypted message.
Ingrid Verbauwhede - One of the best experts on this subject based on the ideXlab platform.
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FPL - Hardware acceleration of a software-based VPN
2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016Co-Authors: Furkan Turan, Ruan De Clercq, Pieter Maene, Oscar Reparaz, Ingrid VerbauwhedeAbstract:A Virtual Private Network (VPN) encrypts and decrypts the private traffic it tunnels over a public network. Maximizing the available bandwidth is an important requirement for network applications, but the Cryptographic Operations add significant computational load to VPN applications, limiting the network throughput. This work presents a coprocessor designed to offer hardware acceleration for these encryption and decryption Operations. The open-source SigmaVPN application is used as the base solution, and a coprocessor is designed for the parts of Networking and Cryptography library (NaCl) which underlies the Cryptographic Operation of SigmaVPN. The hardware-software codesign of this work is implemented on a Xilinx Zynq-7000 SoC, showing a 93% reduction in the execution time of encrypting a 1024-byte frame, and this improved the TCP and UDP communication bandwidths by a factor of 4.36 and 5.36 respectively compared to pure software solution for a 1024-byte frame.
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Hardware acceleration of a software-based VPN
FPL 2016 - 26th International Conference on Field-Programmable Logic and Applications, 2016Co-Authors: Furkan Turan, Ruan De Clercq, Pieter Maene, Oscar Reparaz, Ingrid VerbauwhedeAbstract:A Virtual Private Network (VPN) encrypts and decrypts the private traffic it tunnels over a public network. Maximizing the available bandwidth is an important requirement for network applications, but the Cryptographic Operations add significant computational load to VPN applications, limiting the network throughput. This work presents a coprocessor designed to offer hardware acceleration for these encryption and decryption Operations. The open-source SigmaVPN application is used as the base solution, and a coprocessor is designed for the parts of Networking and Cryptography library (NaCl) which underlies the Cryptographic Operation of SigmaVPN. The hardware-software codesign of this work is implemented on a Xilinx Zynq-7000 SoC, showing a 93% reduction in the execution time of encrypting a 1024-byte frame, and this improved the TCP and UDP communication bandwidths by a factor of 4.36 and 5.36 respectively compared to pure software solution for a 1024-byte frame.
Yohei Kaneko - One of the best experts on this subject based on the ideXlab platform.
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Cryptographic Operation Load-Balancing between Cryptographic Module and CPU
2015 IEEE 29th International Conference on Advanced Information Networking and Applications, 2015Co-Authors: Yohei Kaneko, Takamichi Saito, Hiroaki KikuchiAbstract:Mobile devices such as smartphones and tables have permeated into our daily lives and are now often indispensable because of the constant Internet access they provide. Furthermore, with ever increasing concerns regarding privacy and security, it has become popular to utilize Cryptographic Operations when accessing Web application servers from such devices. However, since such Operations cause high loading on the central processing units (CPUs) of personal computers (PCs) or servers, mobile device CPUs now often come equipped with hardware Cryptographic modules. These Cryptographic modules are frequently utilized by many mobile device applications via a process known as offloading. However, when all Cryptographic Operations can be offloaded to Cryptographic modules, device CPUs may become idle, which is an ineffective use of total computing resources. In this paper, we propose the simultaneous balanced offloading of Cryptographic Operations to the Cryptographic module of an AM3358 processor and CPU via load-balancing and then evaluate the performance of our implementation. We evaluated our proposed system and concluded that while it is capable of working effectively, in most cases files smaller than approximately 1000 bytes can be executed faster via the CPU alone, whereas when files are larger than 1000 bytes, the proposed system is faster. In the case of encrypting or decrypting a 7 Kbyte file, our proposed system is twice as fast as 'CPU only' Operation.
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AINA - Cryptographic Operation Load-Balancing between Cryptographic Module and CPU
2015 IEEE 29th International Conference on Advanced Information Networking and Applications, 2015Co-Authors: Yohei Kaneko, Takamichi Saito, Hiroaki KikuchiAbstract:Mobile devices such as smartphones and tables have permeated into our daily lives and are now often indispensable because of the constant Internet access they provide. Furthermore, with ever increasing concerns regarding privacy and security, it has become popular to utilize Cryptographic Operations when accessing Web application servers from such devices. However, since such Operations cause high loading on the central processing units (CPUs) of personal computers (PCs) or servers, mobile device CPUs now often come equipped with hardware Cryptographic modules. These Cryptographic modules are frequently utilized by many mobile device applications via a process known as offloading. However, when all Cryptographic Operations can be offloaded to Cryptographic modules, device CPUs may become idle, which is an ineffective use of total computing resources. In this paper, we propose the simultaneous balanced offloading of Cryptographic Operations to the Cryptographic module of an AM3358 processor and CPU via load-balancing and then evaluate the performance of our implementation. We evaluated our proposed system and concluded that while it is capable of working effectively, in most cases files smaller than approximately 1000 bytes can be executed faster via the CPU alone, whereas when files are larger than 1000 bytes, the proposed system is faster. In the case of encrypting or decrypting a 7 Kbyte file, our proposed system is twice as fast as 'CPU only' Operation.
William Marnane - One of the best experts on this subject based on the ideXlab platform.
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SoCC - A low-power pairing-based Cryptographic accelerator for embedded security applications
2009 IEEE International SOC Conference (SOCC), 2009Co-Authors: Tom English, Michel Schellekens, Maurice Keller, Ka Lok Man, Emanuel Popovici, William MarnaneAbstract:We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve Cryptographic Operation called the Tate Pairing over the field GF(2251). In this paper, we describe the implementation of the design in TSMC 65nm GP CMOS standard cells and the optimisations made for low-power Operation. The resulting core computes the pairing in 1.5ms and consumes less than 4mW.
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A low-power pairing-based Cryptographic accelerator for embedded security applications
Proceedings - IEEE International SOC Conference, SOCC 2009, 2009Co-Authors: Tom English, Michel Schellekens, Maurice Keller, Ka Lok Man, Emanuel Popovici, William MarnaneAbstract:We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve Cryptographic Operation called the Tate Pairing over the field GF(2251). In this paper, we describe the implementation of the design in TSMC 65 nm GP CMOS standard cells and the optimisations made for low-power Operation. The resulting core computes the pairing in 1.5 ms and consumes less than 4 mW.
Ohyoung Song - One of the best experts on this subject based on the ideXlab platform.
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ISPA - Power-Efficient Architecture of Zigbee Security Processing
2008 IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008Co-Authors: Ohyoung SongAbstract:In general, the Cryptographic Operation in wireless devices which have low memory and low computing power causes the system overhead, so that it badly affects the performance of other tasks. Therefore, it is positively necessary to implement the security hardware which is dedicated to the Cryptographic Operation. Early researches about the security hardware architectures make design metrics with data throughput, gate usage, and power consumption to demonstrate the efficiency of their architectures. In this paper, we provide an efficient hardware architecture of the security processing for ZigBee, which satisfies the constraints IEEE 802.15.4 standard requires. These requirements mainly consist of the critical response time, the verification delay, and the throughput. In experiments, we implemented the security processing for ZigBee that used fewer logic gates and consumed low power than other earlier ZigBee chips and fulfilled the standard requirements with considerable margins.
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Power-Efficient Architecture of Zigbee Security Processing
2008 IEEE International Symposium on Parallel and Distributed Processing with Applications, 2008Co-Authors: Ohyoung SongAbstract:In general, the Cryptographic Operation in wireless devices which have low memory and low computing power causes the system overhead, so that it badly affects the performance of other tasks. Therefore, it is positively necessary to implement the security hardware which is dedicated to the Cryptographic Operation. Early researches about the security hardware architectures make design metrics with data throughput, gate usage, and power consumption to demonstrate the efficiency of their architectures. In this paper, we provide an efficient hardware architecture of the security processing for ZigBee, which satisfies the constraints IEEE 802.15.4 standard requires. These requirements mainly consist of the critical response time, the verification delay, and the throughput. In experiments, we implemented the security processing for ZigBee that used fewer logic gates and consumed low power than other earlier ZigBee chips and fulfilled the standard requirements with considerable margins.