The Experts below are selected from a list of 321 Experts worldwide ranked by ideXlab platform
Makoto Takamiya - One of the best experts on this subject based on the ideXlab platform.
-
a low power cmos Crystal Oscillator using a stacked amplifier architecture
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Shunta Iguchi, Takayasu Sakurai, Makoto TakamiyaAbstract:This paper presents a low-power 39.25-MHz Crystal Oscillator with a new stacked-amplifier architecture achieving the smallest figure of merit (FoM) ever reported for a Crystal Oscillator for wireless communications. Theoretical analyses of the power consumption and the phase noise (PN) in the proposed stacked-amplifier architecture are newly provided to clarify the reason why the proposed stacked-amplifier architecture achieves the smallest FoM. Additionally, a new self-forward-body-biasing technique and flicker noise suppression technique are shown to reduce the minimum operational supply voltage (VDD(MIN)) and the PN, respectively. The proposed 3.3-V, 39.25-MHz stacked-amplifier Crystal Oscillator fabricated in a 65-nm CMOS process exhibits the smallest FoM for a Crystal Oscillator of −248 dBc/Hz with a power consumption of 19 $\mu \text{W}$ and PN of −139 dBc/Hz at 1-kHz offset frequency. The relative frequency errors among 11 samples at temperatures of −30 °C to 80 °C and for ±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm, respectively. The long-term frequency error is −0.98 ppm in the first year (=365 days).
-
A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Shunta Iguchi, Takayasu Sakurai, Makoto TakamiyaAbstract:This paper presents a low-power 39.25-MHz Crystal Oscillator with a new stacked-amplifier architecture achieving the smallest figure of merit (FoM) ever reported for a Crystal Oscillator for wireless communications. Theoretical analyses of the power consumption and the phase noise (PN) in the proposed stacked-amplifier architecture are newly provided to clarify the reason why the proposed stacked-amplifier architecture achieves the smallest FoM. Additionally, a new self-forward-body-biasing technique and flicker noise suppression technique are shown to reduce the minimum operational supply voltage (VDD(MIN)) and the PN, respectively. The proposed 3.3-V, 39.25-MHz stackedamplifier Crystal Oscillator fabricated in a 65-nm CMOS process exhibits the smallest FoM for a Crystal Oscillator of -248 dBc/Hz with a power consumption of 19 μW and PN of -139 dBc/Hz at 1-kHz offset frequency. The relative frequency errors among 11 samples at temperatures of -30 °C to 80 °C and for ±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm, respectively. The long-term frequency error is -0.98 ppm in the first year (=365 days).
-
variation tolerant quick start up cmos Crystal Oscillator with chirp injection and negative resistance booster
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Shunta Iguchi, Takayasu Sakurai, Hiroshi Fuketa, Makoto TakamiyaAbstract:This paper presents a variation-tolerant quick-start-up 39.25 MHz Crystal Oscillator and a theoretical analysis of a proposed chirp injector (CI) and negative resistance booster (NRB) for the quick start up. A new analysis of the theoretical minimum start-up time provides a new criterion for evaluating the start-up time in Crystal Oscillators. The calculated theoretical minimum start-up time at 39.25 MHz is ${11}.{1}\ {\upmu }{s}$ . A new analysis of the proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI and NRB reduce the start-up time and its variation. The proposed Crystal Oscillator with the proposed CI and NRB exhibits a start-up time of 158 μs at 39.25 MHz. The variation of the start-up time variations is ${\pm}{13}\% $ over the supply voltage range of 1.2–1.8 V and ${\pm }{7}\% $ over the temperature range of $- {30}\text{ to } {125}\;^\circ {\rm C}$ . The power consumption of the Crystal Oscillator in the steady state is 181 μW with a phase noise of $- {147}\;{\bf{dBc}}/{\bf{Hz}}$ at 1 kHz offset frequency, which corresponds to a figure of merit (FoM) of 276 dB.
-
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Shunta Iguchi, Takayasu Sakurai, Hiroshi Fuketa, Makoto TakamiyaAbstract:This paper presents a variation-tolerant quick-startup 39.25 MHz Crystal Oscillator and a theoretical analysis of a proposed chirp injector (CI) and negative resistance booster (NRB) for the quick start up. A new analysis of the theoretical minimum start-up time provides a new criterion for evaluating the start-up time in Crystal Oscillators. The calculated theoretical minimum start-up time at 39.25 MHz is 11.1 μs. Anew analysis of the proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI and NRB reduce the start-up time and its variation. The proposed Crystal Oscillator with the proposed CI and NRB exhibits a startup time of 158 μs at 39.25 MHz. The variation of the start-up time variations is ±13% over the supply voltage range of 1.2-1.8 V and ±7% over the temperature range of -30 to 125 °C. The power consumption of the Crystal Oscillator in the steady state is 181 μW with a phase noise of -147 dBc/Hz at 1 kHz offset frequency, which corresponds to a figure of merit (FoM) of 276 dB.
-
ISLPED - 0.35V, 4.1μW, 39MHz Crystal Oscillator in 40nm CMOS
Proceedings of the 2012 ACM IEEE international symposium on Low power electronics and design - ISLPED '12, 2012Co-Authors: Akira Saito, Yunfei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto TakamiyaAbstract:A design methodology for sub-0.5V Crystal Oscillators is shown to realize an all-sub-0.5V ultra low power RF transceiver for wireless sensor networks. To reduce the minimum operating voltage (VDDmin) of the Crystal Oscillator, both the optimization of the gate width of the CMOS inverter in the Crystal Oscillator and the reduction in gate length by CMOS technology scaling are required. In accordance with the developed design methodology, a 39MHz Crystal Oscillator is designed and fabricated in a 40nm CMOS. The measured power consumption is 4.1μW at 0.35V and 39MHz, and the power supply voltage is the lowest among the previously reported Crystal Oscillators.
Shunta Iguchi - One of the best experts on this subject based on the ideXlab platform.
-
a low power cmos Crystal Oscillator using a stacked amplifier architecture
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Shunta Iguchi, Takayasu Sakurai, Makoto TakamiyaAbstract:This paper presents a low-power 39.25-MHz Crystal Oscillator with a new stacked-amplifier architecture achieving the smallest figure of merit (FoM) ever reported for a Crystal Oscillator for wireless communications. Theoretical analyses of the power consumption and the phase noise (PN) in the proposed stacked-amplifier architecture are newly provided to clarify the reason why the proposed stacked-amplifier architecture achieves the smallest FoM. Additionally, a new self-forward-body-biasing technique and flicker noise suppression technique are shown to reduce the minimum operational supply voltage (VDD(MIN)) and the PN, respectively. The proposed 3.3-V, 39.25-MHz stacked-amplifier Crystal Oscillator fabricated in a 65-nm CMOS process exhibits the smallest FoM for a Crystal Oscillator of −248 dBc/Hz with a power consumption of 19 $\mu \text{W}$ and PN of −139 dBc/Hz at 1-kHz offset frequency. The relative frequency errors among 11 samples at temperatures of −30 °C to 80 °C and for ±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm, respectively. The long-term frequency error is −0.98 ppm in the first year (=365 days).
-
A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Shunta Iguchi, Takayasu Sakurai, Makoto TakamiyaAbstract:This paper presents a low-power 39.25-MHz Crystal Oscillator with a new stacked-amplifier architecture achieving the smallest figure of merit (FoM) ever reported for a Crystal Oscillator for wireless communications. Theoretical analyses of the power consumption and the phase noise (PN) in the proposed stacked-amplifier architecture are newly provided to clarify the reason why the proposed stacked-amplifier architecture achieves the smallest FoM. Additionally, a new self-forward-body-biasing technique and flicker noise suppression technique are shown to reduce the minimum operational supply voltage (VDD(MIN)) and the PN, respectively. The proposed 3.3-V, 39.25-MHz stackedamplifier Crystal Oscillator fabricated in a 65-nm CMOS process exhibits the smallest FoM for a Crystal Oscillator of -248 dBc/Hz with a power consumption of 19 μW and PN of -139 dBc/Hz at 1-kHz offset frequency. The relative frequency errors among 11 samples at temperatures of -30 °C to 80 °C and for ±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm, respectively. The long-term frequency error is -0.98 ppm in the first year (=365 days).
-
variation tolerant quick start up cmos Crystal Oscillator with chirp injection and negative resistance booster
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Shunta Iguchi, Takayasu Sakurai, Hiroshi Fuketa, Makoto TakamiyaAbstract:This paper presents a variation-tolerant quick-start-up 39.25 MHz Crystal Oscillator and a theoretical analysis of a proposed chirp injector (CI) and negative resistance booster (NRB) for the quick start up. A new analysis of the theoretical minimum start-up time provides a new criterion for evaluating the start-up time in Crystal Oscillators. The calculated theoretical minimum start-up time at 39.25 MHz is ${11}.{1}\ {\upmu }{s}$ . A new analysis of the proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI and NRB reduce the start-up time and its variation. The proposed Crystal Oscillator with the proposed CI and NRB exhibits a start-up time of 158 μs at 39.25 MHz. The variation of the start-up time variations is ${\pm}{13}\% $ over the supply voltage range of 1.2–1.8 V and ${\pm }{7}\% $ over the temperature range of $- {30}\text{ to } {125}\;^\circ {\rm C}$ . The power consumption of the Crystal Oscillator in the steady state is 181 μW with a phase noise of $- {147}\;{\bf{dBc}}/{\bf{Hz}}$ at 1 kHz offset frequency, which corresponds to a figure of merit (FoM) of 276 dB.
-
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Shunta Iguchi, Takayasu Sakurai, Hiroshi Fuketa, Makoto TakamiyaAbstract:This paper presents a variation-tolerant quick-startup 39.25 MHz Crystal Oscillator and a theoretical analysis of a proposed chirp injector (CI) and negative resistance booster (NRB) for the quick start up. A new analysis of the theoretical minimum start-up time provides a new criterion for evaluating the start-up time in Crystal Oscillators. The calculated theoretical minimum start-up time at 39.25 MHz is 11.1 μs. Anew analysis of the proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI and NRB reduce the start-up time and its variation. The proposed Crystal Oscillator with the proposed CI and NRB exhibits a startup time of 158 μs at 39.25 MHz. The variation of the start-up time variations is ±13% over the supply voltage range of 1.2-1.8 V and ±7% over the temperature range of -30 to 125 °C. The power consumption of the Crystal Oscillator in the steady state is 181 μW with a phase noise of -147 dBc/Hz at 1 kHz offset frequency, which corresponds to a figure of merit (FoM) of 276 dB.
Akira Matsuzawa - One of the best experts on this subject based on the ideXlab platform.
-
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier
2018 IEEE Symposium on VLSI Circuits, 2018Co-Authors: Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira MatsuzawaAbstract:This paper presents a low-energy and quick start-up 26/40 MHz Crystal Oscillator for IoT wireless communications. The negative resistance is boosted to reduce the start-up time by using a reconfigurable multi-stage amplifier during the start-up period. A variable feedforward path implemented in the multi stage amplifier can overcome a conventional limitation of the negative resistance. At 40 MHz oscillation, the proposed Crystal Oscillator fabricated in 65 nm CMOS demonstrates a start-up energy and time of 37.2 nJ and 64 μs, respectively.
-
a 64μs start up 26 40mhz Crystal Oscillator with negative resistance boosting technique using reconfigurable multi stage amplifier
Symposium on VLSI Circuits, 2018Co-Authors: Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira MatsuzawaAbstract:This paper presents a low-energy and quick start-up 26/40 MHz Crystal Oscillator for IoT wireless communications. The negative resistance is boosted to reduce the start-up time by using a reconfigurable multi-stage amplifier during the start-up period. A variable feedforward path implemented in the multi stage amplifier can overcome a conventional limitation of the negative resistance. At 40 MHz oscillation, the proposed Crystal Oscillator fabricated in 65 nm CMOS demonstrates a start-up energy and time of 37.2 nJ and 64 μs, respectively.
Takayasu Sakurai - One of the best experts on this subject based on the ideXlab platform.
-
a low power cmos Crystal Oscillator using a stacked amplifier architecture
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Shunta Iguchi, Takayasu Sakurai, Makoto TakamiyaAbstract:This paper presents a low-power 39.25-MHz Crystal Oscillator with a new stacked-amplifier architecture achieving the smallest figure of merit (FoM) ever reported for a Crystal Oscillator for wireless communications. Theoretical analyses of the power consumption and the phase noise (PN) in the proposed stacked-amplifier architecture are newly provided to clarify the reason why the proposed stacked-amplifier architecture achieves the smallest FoM. Additionally, a new self-forward-body-biasing technique and flicker noise suppression technique are shown to reduce the minimum operational supply voltage (VDD(MIN)) and the PN, respectively. The proposed 3.3-V, 39.25-MHz stacked-amplifier Crystal Oscillator fabricated in a 65-nm CMOS process exhibits the smallest FoM for a Crystal Oscillator of −248 dBc/Hz with a power consumption of 19 $\mu \text{W}$ and PN of −139 dBc/Hz at 1-kHz offset frequency. The relative frequency errors among 11 samples at temperatures of −30 °C to 80 °C and for ±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm, respectively. The long-term frequency error is −0.98 ppm in the first year (=365 days).
-
A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture
IEEE Journal of Solid-State Circuits, 2017Co-Authors: Shunta Iguchi, Takayasu Sakurai, Makoto TakamiyaAbstract:This paper presents a low-power 39.25-MHz Crystal Oscillator with a new stacked-amplifier architecture achieving the smallest figure of merit (FoM) ever reported for a Crystal Oscillator for wireless communications. Theoretical analyses of the power consumption and the phase noise (PN) in the proposed stacked-amplifier architecture are newly provided to clarify the reason why the proposed stacked-amplifier architecture achieves the smallest FoM. Additionally, a new self-forward-body-biasing technique and flicker noise suppression technique are shown to reduce the minimum operational supply voltage (VDD(MIN)) and the PN, respectively. The proposed 3.3-V, 39.25-MHz stackedamplifier Crystal Oscillator fabricated in a 65-nm CMOS process exhibits the smallest FoM for a Crystal Oscillator of -248 dBc/Hz with a power consumption of 19 μW and PN of -139 dBc/Hz at 1-kHz offset frequency. The relative frequency errors among 11 samples at temperatures of -30 °C to 80 °C and for ±10% supply voltage variation are ±10.5 ppm and ±0.12 ppm, respectively. The long-term frequency error is -0.98 ppm in the first year (=365 days).
-
variation tolerant quick start up cmos Crystal Oscillator with chirp injection and negative resistance booster
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Shunta Iguchi, Takayasu Sakurai, Hiroshi Fuketa, Makoto TakamiyaAbstract:This paper presents a variation-tolerant quick-start-up 39.25 MHz Crystal Oscillator and a theoretical analysis of a proposed chirp injector (CI) and negative resistance booster (NRB) for the quick start up. A new analysis of the theoretical minimum start-up time provides a new criterion for evaluating the start-up time in Crystal Oscillators. The calculated theoretical minimum start-up time at 39.25 MHz is ${11}.{1}\ {\upmu }{s}$ . A new analysis of the proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI and NRB reduce the start-up time and its variation. The proposed Crystal Oscillator with the proposed CI and NRB exhibits a start-up time of 158 μs at 39.25 MHz. The variation of the start-up time variations is ${\pm}{13}\% $ over the supply voltage range of 1.2–1.8 V and ${\pm }{7}\% $ over the temperature range of $- {30}\text{ to } {125}\;^\circ {\rm C}$ . The power consumption of the Crystal Oscillator in the steady state is 181 μW with a phase noise of $- {147}\;{\bf{dBc}}/{\bf{Hz}}$ at 1 kHz offset frequency, which corresponds to a figure of merit (FoM) of 276 dB.
-
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Shunta Iguchi, Takayasu Sakurai, Hiroshi Fuketa, Makoto TakamiyaAbstract:This paper presents a variation-tolerant quick-startup 39.25 MHz Crystal Oscillator and a theoretical analysis of a proposed chirp injector (CI) and negative resistance booster (NRB) for the quick start up. A new analysis of the theoretical minimum start-up time provides a new criterion for evaluating the start-up time in Crystal Oscillators. The calculated theoretical minimum start-up time at 39.25 MHz is 11.1 μs. Anew analysis of the proposed CI and NRB clarifies the validity of the universal optimum control method. It explains the reason why the proposed CI and NRB reduce the start-up time and its variation. The proposed Crystal Oscillator with the proposed CI and NRB exhibits a startup time of 158 μs at 39.25 MHz. The variation of the start-up time variations is ±13% over the supply voltage range of 1.2-1.8 V and ±7% over the temperature range of -30 to 125 °C. The power consumption of the Crystal Oscillator in the steady state is 181 μW with a phase noise of -147 dBc/Hz at 1 kHz offset frequency, which corresponds to a figure of merit (FoM) of 276 dB.
-
ISLPED - 0.35V, 4.1μW, 39MHz Crystal Oscillator in 40nm CMOS
Proceedings of the 2012 ACM IEEE international symposium on Low power electronics and design - ISLPED '12, 2012Co-Authors: Akira Saito, Yunfei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto TakamiyaAbstract:A design methodology for sub-0.5V Crystal Oscillators is shown to realize an all-sub-0.5V ultra low power RF transceiver for wireless sensor networks. To reduce the minimum operating voltage (VDDmin) of the Crystal Oscillator, both the optimization of the gate width of the CMOS inverter in the Crystal Oscillator and the reduction in gate length by CMOS technology scaling are required. In accordance with the developed design methodology, a 39MHz Crystal Oscillator is designed and fabricated in a 40nm CMOS. The measured power consumption is 4.1μW at 0.35V and 39MHz, and the power supply voltage is the lowest among the previously reported Crystal Oscillators.
Masaya Miyahara - One of the best experts on this subject based on the ideXlab platform.
-
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier
2018 IEEE Symposium on VLSI Circuits, 2018Co-Authors: Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira MatsuzawaAbstract:This paper presents a low-energy and quick start-up 26/40 MHz Crystal Oscillator for IoT wireless communications. The negative resistance is boosted to reduce the start-up time by using a reconfigurable multi-stage amplifier during the start-up period. A variable feedforward path implemented in the multi stage amplifier can overcome a conventional limitation of the negative resistance. At 40 MHz oscillation, the proposed Crystal Oscillator fabricated in 65 nm CMOS demonstrates a start-up energy and time of 37.2 nJ and 64 μs, respectively.
-
a 64μs start up 26 40mhz Crystal Oscillator with negative resistance boosting technique using reconfigurable multi stage amplifier
Symposium on VLSI Circuits, 2018Co-Authors: Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira MatsuzawaAbstract:This paper presents a low-energy and quick start-up 26/40 MHz Crystal Oscillator for IoT wireless communications. The negative resistance is boosted to reduce the start-up time by using a reconfigurable multi-stage amplifier during the start-up period. A variable feedforward path implemented in the multi stage amplifier can overcome a conventional limitation of the negative resistance. At 40 MHz oscillation, the proposed Crystal Oscillator fabricated in 65 nm CMOS demonstrates a start-up energy and time of 37.2 nJ and 64 μs, respectively.