Cycle Path

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Wei Yu - One of the best experts on this subject based on the ideXlab platform.

  • New LP Relaxations for Minimum Cycle/Path/Tree Cover Problems
    Theoretical Computer Science, 2020
    Co-Authors: Wei Yu
    Abstract:

    Abstract Given an undirected complete graph G = ( V , E ) with nonnegative edge weight function obeying the triangle inequality, a set { C 1 , C 2 , … , C k } of Cycles is called a Cycle cover if V ⊆ ⋃ i = 1 k V ( C i ) , where V ( C i ) represents the set of vertices in C i , and its cost is given by the maximum weight of the Cycles. The Minimum Cycle Cover Problem (MCCP) aims to find a Cycle cover of cost at most λ with the minimum number of Cycles. We propose new LP relaxations for MCCP as well as its variants, called the Minimum Path Cover Problem (MPCP) and the Minimum Tree Cover Problem, where the Cycles are replaced by Paths or trees. Moreover, we give new LP relaxations for a special case of the rooted version of MCCP/MPCP. We show that these LP relaxations have significantly better integrality gaps than the previous relaxations.

  • AAIM - New LP Relaxations for Minimum Cycle/Path/Tree Cover Problems
    Algorithmic Aspects in Information and Management, 2018
    Co-Authors: Wei Yu
    Abstract:

    Given an undirected complete weighted graph \(G=(V,E)\) with nonnegative weight function obeying the triangle inequality, a set \(\{C_1,C_2,\) \(\ldots ,C_k\}\) of Cycles is called a Cycle cover if \(V \subseteq \bigcup _{i=1}^k V(C_i)\) and its cost is given by the maximum weight of the Cycles. The Minimum Cycle Cover Problem (MCCP) aims to find a Cycle cover of cost at most \(\lambda \) with the minimum number of Cycles. We propose new LP relaxations for MCCP as well as its variants, called the Minimum Path Cover Problem (MPCP) and the Minimum Tree Cover Problem, where the Cycles are replaced by Paths or trees. Moreover, we give new LP relaxations for a special case of the rooted version of MCCP/MPCP and show that these LP relaxations have significantly better integrality gaps than the previous relaxations.

  • Better approximability results for min–max tree/Cycle/Path cover problems
    Journal of Combinatorial Optimization, 2018
    Co-Authors: Wei Yu, Zhaohui Liu
    Abstract:

    We study the problem of covering the vertices of an undirected weighted graph with a given number of trees (Cycles, Paths) to minimize the weight of the maximum weight tree (Cycle, Path). Improved inapproximability lower bounds are proved and better approximation algorithms are designed for several variants of this problem.

  • COCOON - Better Inapproximability Bounds and Approximation Algorithms for Min-Max Tree/Cycle/Path Cover Problems
    Lecture Notes in Computer Science, 2017
    Co-Authors: Wei Yu
    Abstract:

    We study the problem of covering the vertices of an undirected weighted graph with a given number of trees (Cycles, Paths) to minimize the weight of the maximum weight tree (Cycle, Path). Improved inapproximability lower bounds are proved and better approximation algorithms are designed for several variants of this problem.

  • Better Inapproximability Bounds and Approximation Algorithms for Min-Max Tree/Cycle/Path Cover Problems
    Computing and Combinatorics, 2017
    Co-Authors: Wei Yu, Zhaohui Liu
    Abstract:

    We study the problem of covering the vertices of an undirected weighted graph with a given number of trees (Cycles, Paths) to minimize the weight of the maximum weight tree (Cycle, Path). Improved inapproximability lower bounds are proved and better approximation algorithms are designed for several variants of this problem.

Hiroyuki Higuchi - One of the best experts on this subject based on the ideXlab platform.

  • enhancing the performance of multi Cycle Path analysis in an industrial setting
    Asia and South Pacific Design Automation Conference, 2004
    Co-Authors: Hiroyuki Higuchi, Yusuke Matsunaga
    Abstract:

    In this paper we enhance the performance of multi-Cycle Path analysis in an industrial setting. Industrial designs are, in general, more complicated, but contain more information than fundamental sequential circuits. We show how such information is used for improving the quality and the efficiency of multi-Cycle Path analysis. Specifically, we propose local FSM learning to take into account reachability information. We also propose FF enable learning to accelerate multi-Cycle Path analysis. Experimental results show that our methods can handle large industrial designs with tens of thousands of FFs and detects more multi-Cycle Paths faster than conventional ones.

  • ASP-DAC - Enhancing the performance of multi-Cycle Path analysis in an industrial setting
    ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004
    Co-Authors: Hiroyuki Higuchi, Yusuke Matsunaga
    Abstract:

    In this paper we enhance the performance of multi-Cycle Path analysis in an industrial setting. Industrial designs are, in general, more complicated, but contain more information than fundamental sequential circuits. We show how such information is used for improving the quality and the efficiency of multi-Cycle Path analysis. Specifically, we propose local FSM learning to take into account reachability information. We also propose FF enable learning to accelerate multi-Cycle Path analysis. Experimental results show that our methods can handle large industrial designs with tens of thousands of FFs and detects more multi-Cycle Paths faster than conventional ones.

  • Enhancing the performance of multi-Cycle Path analysis in an industrial setting
    ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 2004
    Co-Authors: Hiroyuki Higuchi, Yusuke Matsunaga
    Abstract:

    We enhance the performance of multiCycle Path analysis in an industrial setting. Industrial designs are, in general, more complicated, but contain more information than fundamental sequential circuits. We show how such information is used for improving the quality and the efficiency of multiCycle Path analysis. Specifically, we propose local FSM learning to take into account reachability information. We also propose FF enable learning to accelerate multiCycle Path analysis. Experimental results show that our methods can handle large industrial designs with tens of thousands of FFs and detects more multiCycle Paths faster than conventional ones.

  • An implication-based method to detect multi-Cycle Paths in large sequential circuits
    Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324), 2002
    Co-Authors: Hiroyuki Higuchi
    Abstract:

    This paper proposes a fast multi-Cycle Path analysis method for large sequential circuits. It determines whether or not all the Paths between every flip-flop pair are multi-Cycle Paths. The proposed method is based on ATPG techniques, especially on implication techniques, to utilize circuit structure and multi-Cycle Path condition directly. The method also checks whether or not the multi-Cycle Path may be invalidated by static hazards in combinational logic parts. Experimental results show that our method is much faster than conventional ones.

  • DAC - An implication-based method to detect multi-Cycle Paths in large sequential circuits
    Proceedings of the 39th conference on Design automation - DAC '02, 2002
    Co-Authors: Hiroyuki Higuchi
    Abstract:

    This paper proposes a fast multi-Cycle Path analysis method for large sequential circuits. It determines whether or not all the Paths between every flip-flop pair are multi-Cycle Paths. The proposed method is based on ATPG techniques, especially on implication techniques, to utilize circuit structure and multi-Cycle Path condition directly. The method also checks whether or not the multi-Cycle Path may be invalidated by static hazards in combinational logic parts. Experimental results show that our method is much faster than conventional ones.

S. Chakravarty - One of the best experts on this subject based on the ideXlab platform.

  • Path delay fault simulation on large industrial designs
    24th IEEE VLSI Test Symposium, 2006
    Co-Authors: S. Natarajan, S. Patil, S. Chakravarty
    Abstract:

    Path delay fault simulation performance on multi-Cycle delay Paths common in industrial designs is discussed using Paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel multi-Cycle Path delay fault simulator. Our experiments show that Path delay fault simulation run-time grows linearly with Path list size. Contrary to commonly held notion that Path delay fault simulation is more expensive than stuck-at fault simulation, our experiments show that performance of Path delay fault grading is comparable to that of stuck-at fault grading. Finally, we propose and evaluate a heuristic that can improve Path delay fault simulation performance and also aid in selection of tests for speed-limiting Paths.

  • Asian Test Symposium - Untestable Multi-Cycle Path Delay Faults in Industrial Designs
    14th Asian Test Symposium (ATS'05), 2005
    Co-Authors: M. Syal, S. Natarajan, Michael S. Hsiao, S. Chakravarty
    Abstract:

    The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across latches results in signals which propagate across multiple clock Cycles along Paths with multiple latches. These Paths need to be tested for delay failures to ensure reliability of performance. However, many of these multi-Cycle Paths can be untestable and significant computational effort is wasted in targeting such Paths during test generation and fault grading. To save this computational effort, a-priori identification of untestable multiCycle Paths is desired. We address this issue in our paper through a novel and unique framework: unlike traditional techniques, which focus only on single-Cycle Path delay faults (for flip-flop based designs with single clock), our framework efficiently identifies untestable multi-Cycle Path delay faults (Mpdfs) in latch-based designs with multiple clocks. We use a novel graphical representation and sequential implications to identify non-robustly untestable M-pdfs through a three-step methodology. Results for industrial designs demonstrate the effectiveness and scalability of our framework.

  • Untestable Multi-Cycle Path Delay Faults in Industrial Designs
    14th Asian Test Symposium (ATS'05), 2005
    Co-Authors: M. Syal, S. Natarajan, S. Chakravarty
    Abstract:

    The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across latches results in signals which propagate across multiple clock Cycles along Paths with multiple latches. These Paths need to be tested for delay failures to ensure reliability of performance. However, many of these multi-Cycle Paths can be untestable and significant computational effort is wasted in targeting such Paths during test generation and fault grading. To save this computational effort, a-priori identification of untestable multiCycle Paths is desired. We address this issue in our paper through a novel and unique framework: unlike traditional techniques, which focus only on single-Cycle Path delay faults (for flip-flop based designs with single clock), our framework efficiently identifies untestable multi-Cycle Path delay faults (Mpdfs) in latch-based designs with multiple clocks. We use a novel graphical representation and sequential implications to identify non-robustly untestable M-pdfs through a three-step methodology. Results for industrial designs demonstrate the effectiveness and scalability of our framework.

Miguel Székely - One of the best experts on this subject based on the ideXlab platform.

  • Analyzing Upper Secondary Education Dropout in Latin America through a Cohort Approach.
    Journal of Education and Learning, 2017
    Co-Authors: Raja Bentaouet Kattan, Miguel Székely
    Abstract:

    This study examines recent trends and factors in school dropout at the upper secondary education level across Latin America. The methodology employs repeated cross sections of data to track the life Cycle Path of cohorts of individuals in 18 countries. A key finding is that while upper secondary enrollment rates increased in the region, dropout has remained persistently high, despite relatively favorable macroeconomic conditions. To explain dropout trends, the study examines the impact of three groups of factors: (i) shifts in the cohort size and socioeconomic composition of the population eligible for entering upper secondary; (b) the macroeconomic environment and labor market opportunities; and (c) the returns to schooling. We show that an important factor in persistently high dropout rates has been the higher numbers of students from poor socioeconomic backgrounds reaching upper secondary. In addition, high returns to education have been a pull factor into schooling, while, especially in countries where the majority of youth dropout prior to upper secondary, the data confirm an apparent substitution effect due to the opportunity cost of forgoing employment opportunities. The findings confirm the growing policy focus on upper secondary across Latin America and suggest implications for the policy agenda.

  • Analyzing the Dynamics of School Dropout in Upper Secondary Education in Latin America: A Cohort Approach - Analyzing the Dynamics of School Dropout in Upper Secondary Education in Latin America: A Cohort Approach
    Policy Research Working Papers, 2015
    Co-Authors: Raja Bentaouet Kattan, Miguel Székely
    Abstract:

    This study examines trends in school dropout at the upper secondary education level across Latin America over the past two decades, and attempts to identify factors influencing these rates. The methodology contributes to the existing literature by employing repeated cross sections of data to track the life Cycle Path of representative groups of individuals belonging to a birth cohort, by constructing and analyzing a synthetic data base of household survey data from 18 countries. A key finding is that while upper secondary enrollment rates increased in the region, the proportion of upper secondary age youth dropping out of school has remained persistently high, despite relatively favorable macroeconomic conditions. Furthermore, the study traces the moment in the life Cycle at which the majority of dropout takes place to reveal differences between countries. Finally, to explain the trends in upper secondary dropout rates, the study examines the impact of three groups of factors: (i) shifts in the cohort size and socioeconomic composition of the population eligible for entering upper secondary education; (b) the macroeconomic environment and labor market opportunities; and (c) the returns to schooling. A series of regressions shows that an important factor that may be driving higher dropout levels has been the higher numbers of students from poor socioeconomic backgrounds reaching the upper secondary level. In addition, high returns to education have been a pull factor into the schooling system, while, especially in countries where the majority of youth dropout early (prior to upper secondary education), the data confirm an apparent substitution effect due to the opportunity cost of forgoing employment opportunities. Overall, the findings confirm the importance of policy makers' focus on upper secondary education across Latin America and suggest implications for focusing the policy agenda.

Zhaohui Liu - One of the best experts on this subject based on the ideXlab platform.