The Experts below are selected from a list of 288 Experts worldwide ranked by ideXlab platform
Kwang-ting Cheng - One of the best experts on this subject based on the ideXlab platform.
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Gate-level test generation for Sequential Circuits
ACM Transactions on Design Automation of Electronic Systems, 1996Co-Authors: Kwang-ting ChengAbstract:This paper discusses the gate-level automatic test pattern generation (ATPG) methods and techniques for Sequential Circuits. The basic concepts, examples, advantages, and limitations of representative methods are reviewed in detail. The relationship between gate-level Sequential circuit ATPG and the partial scan design is also discussed.
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transition fault testing for Sequential Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1993Co-Authors: Kwang-ting ChengAbstract:Addresses the problem of simulating and generating tests for transition faults in nonscan and partial scan synchronous Sequential Circuits. A transition fault model for Sequential Circuits is first proposed. In this fault model, a transition fault is characterized by the fault site, the fault type, and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. Fault simulation and test generation algorithms for this fault model are presented. The fault simulation algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. Experimental results show that neither a comprehensive functional verification sequence nor a test sequence generated by a Sequential circuit test generator for stuck faults produces a high fault coverage for transition faults. Deterministic test generation for transition faults is required to raise the coverage to a reasonable level. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck fault test generation algorithm with some modifications. Experimental results for ISCAS-89 benchmark Circuits and some AT&T designs are presented. Modifications to test generation and fault simulation algorithms required for partial scan Circuits are presented. Experimental results on large benchmark Circuits show that a high transition fault coverage can be achieved for the partial scan Circuits designed using the cycle breaking technique. >
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ITC - Transition fault simulation for Sequential Circuits
Proceedings International Test Conference 1992, 1992Co-Authors: Kwang-ting ChengAbstract:~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous Sequential Circuits. After presenting the concept of the transition fault modell for Sequential Circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a Sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large Circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or Sequential Circuits has been reported before. In this paper, we address the problem of simulating transition faults in Sequential Circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous Sequential Circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 Sequential benchmark Circuits are presented in Section 5.
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on removing redundancy in Sequential Circuits
Design Automation Conference, 1991Co-Authors: Kwang-ting ChengAbstract:A procedure of removing redundancy in large Sequential Circuits Is proposed. In this procedure, no global reset state is required and no state transition informa- tion is needed. A definition of Sequential redundancy is first given. We show that if a fault is potentially undetectable (p- undetectable), it is Sequentially redundant. An algorithm of identifying p-undetectable faults is then described. For large Circuits, we propose a practical procedure to identify a subset, called feedback-free Sequential redundant faults, of redun- dant faults. In this procedure, a minimal set of signals is selected and assumed fully controllable and observable to con- vert the given circuit into a feedback-free model. Redundan- cies in the feedback-free circuit model are then identified and removed. This procedure could also eliminate redundant flip-flops. Experimental results show that our method SUC- cessfully minimizes the signal count by about 8.4%, in aver- age, on six large MCNC benchmark Sequential Circuits with up to 20K gates and 1700 flip-flops. In some examples, up to 7.8% of the flip-flops is removed without changing the circuit's input/output behavior.
R. Kaibel - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - PARIS: a parallel pattern fault simulator for synchronous Sequential Circuits
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, 1991Co-Authors: N. Gouders, R. KaibelAbstract:The authors describe PARIS, a parallel-pattern fault simulator for synchronous Sequential Circuits. PARIS is based on the well-known approach of parallel pattern single fault propagation for combinational Circuits and features several new techniques. Every single pattern packet is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values minimizes the number of events that must be tracked. Clever circuit partitioning prevents multiple evaluation of the feedback free parts of the circuit, thus reducing the required simulation effort. Experiments show that PARIS runs at a substantially higher asymptotic speed compared with a state-of-the-art fault simulator for synchronous Sequential Circuits. >
Miron Abramovici - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - Critical path tracing in Sequential Circuits
[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers, 1Co-Authors: P. R. Menon, Y. Levendel, Miron AbramoviciAbstract:Critical path tracing has been shown to be faster than traditional fault simulation methods, but it produces pessimistic results in some cases involving reconvergent fanout. It is shown that the pessimistic nature of critical path tracing in combinational Circuits can lead to incorrect results that are not necessarily pessimistic in Sequential Circuits. A modification of the method for removing the approximation is proposed, and a critical path tracing algorithm for synchronous Sequential Circuits is presented. >
N. Gouders - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - PARIS: a parallel pattern fault simulator for synchronous Sequential Circuits
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers, 1991Co-Authors: N. Gouders, R. KaibelAbstract:The authors describe PARIS, a parallel-pattern fault simulator for synchronous Sequential Circuits. PARIS is based on the well-known approach of parallel pattern single fault propagation for combinational Circuits and features several new techniques. Every single pattern packet is simulated by an iterative, event-driven method. Heuristic look-ahead of signal values minimizes the number of events that must be tracked. Clever circuit partitioning prevents multiple evaluation of the feedback free parts of the circuit, thus reducing the required simulation effort. Experiments show that PARIS runs at a substantially higher asymptotic speed compared with a state-of-the-art fault simulator for synchronous Sequential Circuits. >
Hideo Fujiwara - One of the best experts on this subject based on the ideXlab platform.
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Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Journal of Electronic Testing, 2012Co-Authors: Taavi Viilukas, Raimund Ubar, Jaan Raik, Anton Karputkin, Maksim Jenihhin, Hideo FujiwaraAbstract:The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous Sequential Circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in Sequential Circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.
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a new class of Sequential Circuits with acyclic test generation complexity
International Conference on Computer Design, 2006Co-Authors: Chia Yee Ooi, Hideo FujiwaraAbstract:This paper introduces a new class of Sequential Circuits called acyclically testable Sequential Circuits which is wider than the class of acyclic Sequential Circuits but whose test generation complexity is equivalent to that of the acyclic Sequential Circuits. We also present a test generation procedure for acyclically testable Sequential Circuits and elaborate a design-for-test (DFT) method to augment an arbitrary Sequential circuit into an acyclically testable Sequential circuit. Since the class of acyclically testable Sequential Circuits is larger than the class of acyclic Sequential Circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.
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ICCD - A New Class of Sequential Circuits with Acyclic Test Generation Complexity
2006 International Conference on Computer Design, 2006Co-Authors: Chia Yee Ooi, Hideo FujiwaraAbstract:This paper introduces a new class of Sequential Circuits called acyclically testable Sequential Circuits which is wider than the class of acyclic Sequential Circuits but whose test generation complexity is equivalent to that of the acyclic Sequential Circuits. We also present a test generation procedure for acyclically testable Sequential Circuits and elaborate a design-for-test (DFT) method to augment an arbitrary Sequential circuit into an acyclically testable Sequential circuit. Since the class of acyclically testable Sequential Circuits is larger than the class of acyclic Sequential Circuits, the DFT method results in lower area overhead than the partial scan method and still achieves complete fault efficiency. Besides, we show through experiment that the proposed method contributes to lower test application time compared to partial scan method. Moreover, the proposed method allows at-speed testing while the partial scan method does not.
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Classification of Sequential Circuits Based on τk Notation and Its Applications
IEICE Transactions on Information and Systems, 2005Co-Authors: Chia Yee Ooi, Thomas Clouqueur, Hideo FujiwaraAbstract:This paper introduces τk notation to be used to assess test generation complexity of classes of Sequential Circuits. Using τk notation, we reconsider and restate the time complexity of test generation for existing classes of acyclic Sequential Circuits. We also introduce a new DFT method called feedback shift register (FSR) scan design technique, which is extended from the scan design technique. Therefore, for a given Sequential circuit, the corresponding FSR scan designed circuit has always equal or lower area overhead and test application time than the corresponding scan designed circuit. Furthermore, we identify some new classes of Sequential Circuits that contain some cyclic Sequential Circuits, which are τ-equivalent and τ2-bounded. These classes are the l-length-bounded testable Circuits, l-length-bounded validity-identifiable Circuits, t-time-bounded testable Circuits and t-time-bounded validity-identifiable Circuits. In addition, we provide two examples of Circuits belonging to these classes, namely counter-cycle finite state machine realizations and state-shiftable finite state machine realizations. Instead of using a DFT method, a given Sequential circuit described at the finite state machine (FSM) level can be synthesized using another test methodology called synthesis for testability (SFT) into a circuit that belongs to one of the easily testable classes of cyclic Sequential Circuits.
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A new class of Sequential Circuits with combinational test generation complexity
IEEE Transactions on Computers, 2000Co-Authors: Hideo FujiwaraAbstract:We introduce a new class of Sequential Circuits with combinational test generation complexity which we call internally balanced structures. It is shown that Sequential Circuits can be classified by their structure as follows: (Sequential Circuits of acyclic structure) /spl sup/ (Sequential Circuits of internally balanced structure) /spl sup/ (Sequential Circuits of balanced structure) and that internally balanced structures allow test generation with combinational test generation complexity. On the other hand, if finite state machines (FSMs) are classified by their realization possibility, it can be shown that (FSMs which can be realized as a Sequential circuit of acyclic structure)=(FSMs which can be realized as a Sequential circuit of internally balanced structure) /spl sup/ (FSMs which can be realized as a Sequential circuit of balanced structure). Hence, any FSM realizable with acyclic structure can also be realized with internally balanced structure which allows test generation with combinational test generation complexity. In addition, we discuss the definition of test generation possibility with combinational test generation complexity and introduce a new definition which covers the previous narrow definition. Finally, we study applications to design for testability based on the partial scan and to test generation time reduction for Sequential Circuits in general, using characteristics of the internally balanced structures. The experimental results show the effectiveness of this approach.
