The Experts below are selected from a list of 297 Experts worldwide ranked by ideXlab platform
E.k.f. Lee - One of the best experts on this subject based on the ideXlab platform.
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Reconfigurable pipelined Data Converter architecture
Proceedings of the 39th Midwest Symposium on Circuits and Systems, 1Co-Authors: E.k.f. LeeAbstract:A reconfigurable pipelined Data Converter architecture suitable for implementing Field Programmable Mixed analog and digital Array (FPMA) is described. The proposed architecture can be reconfigured to a number of different analog-to-digital Converters and/or digital-analog Converters for a given number of conversion stages with different resolutions.
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ISCAS (4) - A reconfigurable pipelined Data Converter
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1Co-Authors: S. Mortezapour, E.k.f. LeeAbstract:A reconfigurable Data Converter (RDC) for integrating with a FPGA is proposed. The RDC consists of a number of programmable Data Converter cells (PDCCs), which can be programmed to perform basic analog-to-digital and digital-to-analog functions that are required in pipelined Converters. A programmable switching network is then used to group and connect a number of PDCCs to obtain different numbers of ADCs and DACs with different resolutions. When the RDC is integrated with a FPGA, it will provide a low cost solution for realizing low to medium volume mixed signal systems. To demonstrate this concept, a prototype RDC was designed in a 2 /spl mu/m CMOS process and tested by configuring the RDC into different Data Converters.
S. Mortezapour - One of the best experts on this subject based on the ideXlab platform.
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ISCAS (4) - A reconfigurable pipelined Data Converter
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1Co-Authors: S. Mortezapour, E.k.f. LeeAbstract:A reconfigurable Data Converter (RDC) for integrating with a FPGA is proposed. The RDC consists of a number of programmable Data Converter cells (PDCCs), which can be programmed to perform basic analog-to-digital and digital-to-analog functions that are required in pipelined Converters. A programmable switching network is then used to group and connect a number of PDCCs to obtain different numbers of ADCs and DACs with different resolutions. When the RDC is integrated with a FPGA, it will provide a low cost solution for realizing low to medium volume mixed signal systems. To demonstrate this concept, a prototype RDC was designed in a 2 /spl mu/m CMOS process and tested by configuring the RDC into different Data Converters.
Franco Maloberti - One of the best experts on this subject based on the ideXlab platform.
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Validation of Data Converter specifications with behavioral modeling simulations
Measurement, 2002Co-Authors: Franco Maloberti, P. Estrada, Piero Malcovati, A. ValeroAbstract:Abstract The increasing complexity of Data Converter architectures makes it necessary to use behavioral models to simulate electrical performances and to determine the relevant Data Converter features. For this purpose, special input stimuli and specific output Data processing are required. In view of that, it is necessary to offer a specific Data-Converter simulation environment that permit the designer to validate the Data Converter specification and to extract the basic blocks key features before starting the transistor level design. Pointed toward this objective, this paper analyses the most utilized architectures and identifies the basic (active and passive) building blocks used. Behavioral models of such basic blocks are discussed. The proposed behavioral models are then used in a pipeline and a Σ–Δ Converter. Specific routines for the determination of Data Converter parameters are presented. Simulations show how specific features of basic blocks affect the overall performances. Thus, guidelines on how to design the circuit in order to meet specifications are given.
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Speed limitations in CMOS Data Converters with switch selection networks
Microelectronics Journal, 1994Co-Authors: S. Brigati, Franco Maloberti, Guido TorelliAbstract:Abstract This paper presents a design guideline for CMOS Data Converters using switch selection networks. After a demonstration of the intrinsic speed limitation of such architectures due to the high number of analogue switches, simple equations are provided which allow a preliminary speed evaluation and give an initial estimation of the best switch sizing prior to a more accurate design. These equations are then checked by circuit simulation on a specific architectures to show their effectiveness as a ‘rule of thumb’ for Data Converter designers.
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Software tool for design and simulation of Data Converters
Southwest Symposium on Mixed-Signal Design 2003., 1Co-Authors: P. Estrada, Franco MalobertiAbstract:This work presents a simulation environment for the design of Data Converters using behavioral modeling in the MATLAB- SIMULINK platform. This environment utilizes a graphic user interface as a CAD tool to design and simulate different Data Converter architectures. Post-processing analysis tools are included for static and dynamic performance calculation.
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ISCAS (4) - CAD system for design and simulation of Data Converters
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 1Co-Authors: P. Estrada, Franco MalobertiAbstract:This work presents a simulation environment for the design of Data Converters using behavioral modeling in the MATLAB-SIMULINK platform. This environment utilizes a graphic user interface as a CAD tool to design and simulate different Data Converter architectures. Post-processing analysis tools are included for static and dynamic performance calculation.
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Virtual test bench for design and simulation of Data Converters
Proceedings of the 2002 IEEE International Workshop on Behavioral Modeling and Simulation 2002. BMAS 2002., 1Co-Authors: P. Estrada, Franco MalobertiAbstract:This work presents a simulation environment for the design of Data Converters using behavioral modeling and the MATLAB-SIMULINK platform. This environment utilizes a graphic user interface as a CAD tool to design and simulate different Data Converter architectures. Post-processing analysis tools are included for static and dynamic performance calculation.
Walt Kester - One of the best experts on this subject based on the ideXlab platform.
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SECTION 6-4 – Data Converter Voltage References
Data Conversion Handbook, 2005Co-Authors: Walt KesterAbstract:Publisher Summary This chapter discusses Data Converter voltage references. Some ADCs and DACs have internal references, while others do not. Some ADCs use the power supply as a reference. There is little standardization with respect to ADC/DAC voltage references. The op amp isolates the reference element from the output and also provides drive capability. However, this op amp must obey the general laws relating to op amp stability. A suitable op amp buffer might be added between the reference and the Data Converter. There are many good references available that are stable with an output capacitor. An illustration is presented, which summarizes some important considerations for Data Converter references.
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Data Converter AC Errors
Data Conversion Handbook, 2005Co-Authors: Walt Kester, James BryantAbstract:This chapter details the AC (alternating current) errors associated with Data Converters. Most of the errors and specifications apply equally to ADCs (analog-to-digital Converters) and DACs (digital-to-analog Converters), while some are more specific to one or the other. It explains theoretical quantization noise of an ideal N-bit Converter. It summarizes the noise in practical ADCs, equivalent input referred noise, and noise-free (flicker-free) code resolution. The chapter explains different ways of characterizing the dynamic performance of Data Converters such as integral and differential nonlinearity distortion effects that include harmonic distortion, worst harmonic, total harmonic distortion (THD), total harmonic distortion plus noise (THD + N), signal-to-noise-and-distortion ratio (SINAD), signal-to-noise ratio (SNR), and effective number of bits (ENOB). It also explores analog bandwidth, spurious free dynamic range (SFDR), two-tone intermodulation distortion (IMD), second- and third-order intercept points, 1 DB compression point, multitone spurious free dynamic range, wideband CDMA (WCDMA) adjacent channel power ratio (ACPR) and adjacent channel leakage ratio (ADLR), noise power ratio (NPR), noise factor (F), and noise figure (NF) with illustrations. The chapter also briefs about aperture time, aperture delay time, and aperture jitter. It further explains about ADC transient response and overvoltage recovery, ADC sparkle codes, metastable states, and bit error rate (BER). The chapter further discusses DAC dynamic performance, which includes DAC settling time, glitch impulse area, DAC SFDR and SNR, measuring DAC SNR with an analog spectrum analyzer, DAC output spectrum and sin (x)/x frequency roll-off, and oversampling interpolating DACs.
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SECTION 1-2 – Data Converters of the 1950s and 1960s
Data Conversion Handbook, 2005Co-Authors: Walt KesterAbstract:Publisher Summary This chapter discusses about the Data Converters from the period 1950s to 1960s. Till mid-1950s, Data Converters were primarily developed and used within specialized applications, such as the Bell System work on PCM, and message encryption systems of World War II. The commercial usage of Data Converters was equal to nil because the Converters were very expensive, bulky, and dissipated lots of power. The digital computers played a pivotal role in commercial development of ADC. The chapter further discusses about the important developments in the field of Data Converters and the driving factors behind these developments. The transition in electronic circuit designs from vacuum tubes to transistors opened up many new possibilities in Data conversion products. The chapter further explains about major developments in the Data Converters that led to their commercial developments, their pioneers, and their findings. It also briefs about Data Converter architectures.
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SECTION 1-5 – Data Converters of the 1990s
Data Conversion Handbook, 2005Co-Authors: Walt KesterAbstract:Publisher Summary This chapter discusses about Data Converters of the 1990s. It points out that markets influencing Data Converters in the 1990s were even more diverse and demanding than that of 1980s. The communications during this period became a driving force for the development of low cost, low power, and high performance Data Converters in modems, cell phone handsets, and wireless infrastructure (base stations). The chapter also briefs about various trends such as packaging, putting an entire Data acquisition system on a chip, including the input multiplexer, programmable gain amplifier (PGA), sample-and-hold, and the ADC function in the Data Converter market during this period. It further discusses about monolithic DACs (digital-to-analog Converters) and monolithic ADCs (analog-to-digital Converters) of the 1990s with examples. It also summarizes some of the key DAC and ADC developments during the 1990s. The chapter briefs about hybrid and modular DACs and ADCs of the 1990s.
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Data Converters of the 1970s
Data Conversion Handbook, 2005Co-Authors: Walt KesterAbstract:This chapter discusses the history and important developments in the field of Data Converters in 1970s and its advantages. The increased availability of low-cost computing technology generated a desire to take advantage of the increased performance and analysis, and therefore, the need for compatible Data Converters. The chapter also briefs about different companies and their contribution to the Data Converter field. It also briefs about the launch of Analog Dialogue magazine in 1967, whose initial charter was stated as “A Journal for the Exchange of Operational Amplifier Technology,” and later on broadened to “A Journal for the Exchange of Analog Technology.” The chapter further discusses about monolithic Data Converters during 1970s, which include bipolar process integrated circuit digital-to-analog Converters (IC DACs). The earliest monolithic DACs were made using bipolar process technology; and they included only the basic core of a complete DAC, the array of switches and resistors to set the weight of each bit. It further explains about various Converters such as 1408, DAC08, AD562, and AD565. The chapter also briefs about complementary-symmetry metal-oxide-semiconductor integrated circuit digital-to-analog Converters (CMOS IC DACs) and monolithic analog-to-digital Converters (ADCs) during 1970s and its features. It further explains about hybrid Data Converters and modular Data Converters of the 1970s, the causes behind invention of these Converters, their advantages and various examples of these Converters launched by different companies.
Hannu Tenhunen - One of the best experts on this subject based on the ideXlab platform.
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ISCAS (1) - Performance analysis of sampling switches in voltage and frequency domains using Volterra series
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 1Co-Authors: A. Gothenberg, Hannu TenhunenAbstract:In any Data Converter system, the linearity of the sampling switch is a very critical parameter, especially for wideband sigma-delta modulators. Distortion introduced in the sampling instance directly degrades the quality of the input signal. In this paper we present analyses of a set of sampling switches in the frequency and voltage domains in order to find the most linear type for wide baseband excitation. Volterra series analysis is adopted to find the frequency behavior of the switches. The theoretical results are verified by circuit simulations in a 0.35 /spl mu/m CMOS process. It is found that the bootstrap sampling switch is a very attractive candidate, especially for frequencies near f/sub s//2.
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Modeling and analysis of substrate coupled noise in pipelined Data Converters
2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390), 1Co-Authors: A. Gothenberg, E. Soenen, Hannu TenhunenAbstract:This paper presents methods to model and analyze substrate coupled noise in pipelined Data Converters. The substrate noise models covers substrate types, such as lightly and highly doped substrates, and the analyzes includes the effects on the pipelined Data Converter performance from a variety of noise shielding techniques, such as guarding and wells. Classical approaches to prevent noise are investigated. It is found that in some cases these traditional design rules are no longer suitable and have to be redefined.
