The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Hideo Fujiwara - One of the best experts on this subject based on the ideXlab platform.
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a non scan dft method at register transfer level to achieve complete fault efficiency
Asia and South Pacific Design Automation Conference, 2000Co-Authors: Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo FujiwaraAbstract:This paper presents a non-scan design-for-testability (DFT) method for VLSIs designed at register transfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a Data Path. The controller and the Data Path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods to the controller and the Data Path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified Data Path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.
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non scan design for testable Data Paths using thru operation
Asia and South Pacific Design Automation Conference, 1997Co-Authors: K Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo FujiwaraAbstract:We present a new non-scan DFT technique for register-transfer (RT) level Data Paths. In the technique, we add thru operations to some operational modules to make the Data Path easily testable. We define a testable measure, weak testability, and consider the problem to make the Data Path weakly testable with minimum hardware overhead. We also define a measure to estimate the test generation time. Experimental results show the effectiveness of our technique and the proposed measure.
Geoff Kuenning - One of the best experts on this subject based on the ideXlab platform.
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trueerase per file secure deletion for the storage Data Path
Annual Computer Security Applications Conference, 2012Co-Authors: Sarah M Diesburg, Christopher Meyers, Mark Stanovich, Michael J Mitchell, Justin Marshall, Julia Gould, Ani Andy Wang, Geoff KuenningAbstract:The ability to securely delete sensitive Data from electronic storage is becoming important. However, current per-file deletion solutions tend to be limited to a segment of the operating system's storage Data Path or specific to particular file systems or storage media. This paper introduces TrueErase, a holistic secure-deletion framework. Through its design, implementation, verification, and evaluation, TrueErase shows that it is possible to build a legacy-compatible full-storage-Data-Path framework that performs per-file secure deletion and works with common file systems and solid-state storage, while handling common system failures. In addition, this framework can serve as a building block for encryption- and tainting-based secure-deletion systems.
Eby G. Friedman - One of the best experts on this subject based on the ideXlab platform.
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optimal clock skew scheduling tolerant to process variations
Design Automation Conference, 1996Co-Authors: Josè Luis Neves, Eby G. FriedmanAbstract:A methodology is presented in this paper for determining an optimal set of clock Path delays for designing high performance VLSI/ULSI-based clock distribution networks. This methodology emphasizes the use of non-zero clock skew to reduce the system-wide minimum clock period. Although choosing (or scheduling) clock skew values has been previously recognized as an optimization technique for reducing the minimum clock period, difficulty in controlling the delays of the clock Paths due to process parameter variations has limited its effectiveness. In this paper the minimum clock period is reduced using intentional clock skew by calculating a permissible clock skew range for each local Data Path while incorporating process dependent delay values of the clock signal Paths. Graph-based algorithms are presented for determining the minimum clock period and for selecting a range of process tolerant clock skews for each local Data Path in the circuit, respectively. These algorithms have been demonstrated on the ISCAS-89 suite of circuits. Furthermore, examples of clock distribution networks with intentional clock skew are shown to tolerate worst case clock skew variations of up to 30% without causing circuit failure while increasing the system-wide maximum clock frequency by up to 20% over zero skew-based systems.
Toshimitsu Masuzawa - One of the best experts on this subject based on the ideXlab platform.
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a non scan dft method at register transfer level to achieve complete fault efficiency
Asia and South Pacific Design Automation Conference, 2000Co-Authors: Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo FujiwaraAbstract:This paper presents a non-scan design-for-testability (DFT) method for VLSIs designed at register transfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a Data Path. The controller and the Data Path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods to the controller and the Data Path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified Data Path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.
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non scan design for testable Data Paths using thru operation
Asia and South Pacific Design Automation Conference, 1997Co-Authors: K Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo FujiwaraAbstract:We present a new non-scan DFT technique for register-transfer (RT) level Data Paths. In the technique, we add thru operations to some operational modules to make the Data Path easily testable. We define a testable measure, weak testability, and consider the problem to make the Data Path weakly testable with minimum hardware overhead. We also define a measure to estimate the test generation time. Experimental results show the effectiveness of our technique and the proposed measure.
K Takabatake - One of the best experts on this subject based on the ideXlab platform.
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non scan design for testable Data Paths using thru operation
Asia and South Pacific Design Automation Conference, 1997Co-Authors: K Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo FujiwaraAbstract:We present a new non-scan DFT technique for register-transfer (RT) level Data Paths. In the technique, we add thru operations to some operational modules to make the Data Path easily testable. We define a testable measure, weak testability, and consider the problem to make the Data Path weakly testable with minimum hardware overhead. We also define a measure to estimate the test generation time. Experimental results show the effectiveness of our technique and the proposed measure.
