The Experts below are selected from a list of 300 Experts worldwide ranked by ideXlab platform
Suvorova Elena - One of the best experts on this subject based on the ideXlab platform.
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Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for onboard Data management and mass storage device: Components, short paper
2016 International SpaceWire Conference (SpaceWire), 2016Co-Authors: Tatiana Solokhina, Jaroslav Petrichkovich, Alexander Glushkov, Andrey Belyaev, Leonid Menshenin, Fedor Putrya, Sheynin Yuriy, Suvorova ElenaAbstract:The article presents a 180nm CMOS Radiation tolerant heterogeneous Multi-core ASIC MCT-04 as the SoC (System-on-Chip) with built-in multichannel multiprotocol SpaceFibre/ GigaSpaceWire (SpaceWire-RUS standard), SpaceWire based switch for the onboard Data and Mass Storage Device management. The SoC design and architecture support Single-Event-Upset (SEU) fault-tolerant. The MCT-04 embedded networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/ /GigaSpaceWire (SpaceWire-RUS)/SpaceFibre links. Input and processed Data streams transmitted via 1.25 Gbps four multiprotocol SpaceFibre/GigaSpaceWire links with built-in DMA controllers. Two SpaceWire links (ECSS-E-50-12C) provide Data Transfer Bandwidth 2–400 Mbps. The MCT-04 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provides a balance between external and internal Data throughput especially for the multifunctional micro and nanosatellites systems.
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Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for the “intelligent” signals and images processing systems
2014 International SpaceWire Conference (SpaceWire), 2014Co-Authors: Tatiana Solokhina, Jaroslav Petrichkovich, Alexander Glushkov, Leonid Menshenin, Sheynin Yuriy, Ilya Alekseev, Suvorova ElenaAbstract:The article presents a Radiation tolerant heterogeneous Multi-core ASIC MC-30SF6 as the SoC (System-on-Chip) for the onboard “intelligent” signals and images processing systems. MC-30SF6 based on a CMOS 180nm Radiation tolerant library and consists of the five ELVEES IP - cores for the processing and compression Data with extra performance more than 9 GFLOPs. The SoC design and architecture support fault tolerance against SEU errors. SoC has built-in multichannel multiprotocol SpaceFibre/GigaSpaceWire (SpaceWire-RUS standard)/SpaceWire embedded networking subsystem. The networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/GigaSpaceWire/SpaceFibre links. SoC support four ports GigaSpaceWire/two ports SpaceWire switch. Input and processed Data streams transmitted via 1.25 Gbps two multiprotocol SpaceFibre/GigaSpaceWire and four GigaSpaceWire links. Two SpaceWire links (ECSS-E-50-12C) provide Data Transfer Bandwidth from 2 up to 400 Mbps. The MC-30SF6 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provide a balance between ASIC throughput and SoC performance especially for the multifunctional micro and nanosatellites systems.
Tatiana Solokhina - One of the best experts on this subject based on the ideXlab platform.
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Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for onboard Data management and mass storage device: Components, short paper
2016 International SpaceWire Conference (SpaceWire), 2016Co-Authors: Tatiana Solokhina, Jaroslav Petrichkovich, Alexander Glushkov, Andrey Belyaev, Leonid Menshenin, Fedor Putrya, Sheynin Yuriy, Suvorova ElenaAbstract:The article presents a 180nm CMOS Radiation tolerant heterogeneous Multi-core ASIC MCT-04 as the SoC (System-on-Chip) with built-in multichannel multiprotocol SpaceFibre/ GigaSpaceWire (SpaceWire-RUS standard), SpaceWire based switch for the onboard Data and Mass Storage Device management. The SoC design and architecture support Single-Event-Upset (SEU) fault-tolerant. The MCT-04 embedded networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/ /GigaSpaceWire (SpaceWire-RUS)/SpaceFibre links. Input and processed Data streams transmitted via 1.25 Gbps four multiprotocol SpaceFibre/GigaSpaceWire links with built-in DMA controllers. Two SpaceWire links (ECSS-E-50-12C) provide Data Transfer Bandwidth 2–400 Mbps. The MCT-04 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provides a balance between external and internal Data throughput especially for the multifunctional micro and nanosatellites systems.
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Radiation tolerant heterogeneous Multicore “system on chip” with built-in multichannel SpaceFibre switch for the “intelligent” signals and images processing systems
2014 International SpaceWire Conference (SpaceWire), 2014Co-Authors: Tatiana Solokhina, Jaroslav Petrichkovich, Alexander Glushkov, Leonid Menshenin, Sheynin Yuriy, Ilya Alekseev, Suvorova ElenaAbstract:The article presents a Radiation tolerant heterogeneous Multi-core ASIC MC-30SF6 as the SoC (System-on-Chip) for the onboard “intelligent” signals and images processing systems. MC-30SF6 based on a CMOS 180nm Radiation tolerant library and consists of the five ELVEES IP - cores for the processing and compression Data with extra performance more than 9 GFLOPs. The SoC design and architecture support fault tolerance against SEU errors. SoC has built-in multichannel multiprotocol SpaceFibre/GigaSpaceWire (SpaceWire-RUS standard)/SpaceWire embedded networking subsystem. The networking subsystem provides multiple ports for high-rate interconnection with combination of SpaceWire/GigaSpaceWire/SpaceFibre links. SoC support four ports GigaSpaceWire/two ports SpaceWire switch. Input and processed Data streams transmitted via 1.25 Gbps two multiprotocol SpaceFibre/GigaSpaceWire and four GigaSpaceWire links. Two SpaceWire links (ECSS-E-50-12C) provide Data Transfer Bandwidth from 2 up to 400 Mbps. The MC-30SF6 embedded networking subsystem on the base SpaceWire/GigaSpaceWire/SpaceFibre provide a balance between ASIC throughput and SoC performance especially for the multifunctional micro and nanosatellites systems.
Jun Tanida - One of the best experts on this subject based on the ideXlab platform.
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dynamic reconfiguration of differential pixel output for cmos imager dedicated to wdm sdm indoor optical wireless lan
IEEE Photonics Technology Letters, 2009Co-Authors: Keiichiro Kagawa, Jun Ohta, Jun TanidaAbstract:A dedicated complementary metal-oxide-semiconductor (CMOS) imager with parallel photoreceivers has been deployed for new indoor wireless local area network systems where images and communications are mixed to offer location awareness and an extended Data Transfer Bandwidth with wavelength- and space-division multiplexing for the downlink and uplink, respectively. To realize Data acquisition while capturing images, dynamic reconfiguration of differential pixel output with a small area overhead is proposed for suppressing signal contamination at the sensitive photoreceiver circuitry by common mode noise from the image readout digital circuitry. A prototype CMOS imager with 64 times 64 pixels and four parallel photoreceiver channels was fabricated in a standard 0.35-mum CMOS process, and concurrent scene image capturing and multipoint Data acquisition at 10-Mb/s/channel were demonstrated. The measured signal-to-crosstalk ratio was around 18 dB.
Ninghui Sun - One of the best experts on this subject based on the ideXlab platform.
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FCCM - Accelerating Millions of Short Reads Mapping on a Heterogeneous Architecture with FPGA Accelerator
2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2012Co-Authors: Wen Tang, Wendi Wang, Bo Duan, Chunming Zhang, Guangming Tan, Peiheng Zhang, Ninghui SunAbstract:The explosion of Next Generation Sequencing (NGS) Data with over one billion reads per day poses a great challenge to the capability of current computing systems. In this paper, we proposed a CPU-FPGA heterogeneous architecture for accelerating a short reads mapping algorithm, which was built upon the concept of hash-index. In particular, by extracting and mapping the most time-consuming and basic operations to specialized processing elements (PEs), our new algorithm is favorable to efficient acceleration on FPGAs. The proposed architecture is implemented and evaluated on a customized FPGA accelerator card with a Xilinx Virtex5 LX330 FPGA resided. Limited by available Data Transfer Bandwidth, our NGS mapping accelerator, which operates at 175MHz, integrates up to 100 PEs. Compared to an Intel six-cores CPU, the speedup of our accelerator ranges from 22.2 times to 42.9 times.
Ali Ahmadinia - One of the best experts on this subject based on the ideXlab platform.
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distributed deep convolutional neural network for smart camera image recognition
International Conference on Distributed Smart Cameras, 2017Co-Authors: Emmanuel A Castillo, Ali AhmadiniaAbstract:Smart Cameras brought sight to the idea of cameras as sensors for visual Data rather than strictly for taking pictures. One set of applications that leverages this idea are image recognition applications. Unfortunately, a main drawback on these applications is the hardware limitations that they compromise with due to many of its applications residing in the embedded domain. As a matter of fact, a Deep Convolutional Neural Network (DCNN) is the main general algorithm used in handling the image recognition tasks that can be costly in response time, power consumption and Data Transfer Bandwidth. However, the general architecture of a DCNN is consisted of layers that do specific processing tasks. These distribution of layers can be efficiently organized on a system consisted of Smart Cameras that can improve response time, limit power usage and reduce Data Transfer Bandwidth. A concept is proposed to distribute the layers of a DCNN within a distributed set of Smart Cameras on embedded devices, an edge device and the Cloud that may improve response time, power consumption and Data Transfer Bandwidth.
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ICDSC - Distributed Deep Convolutional Neural Network For Smart Camera Image Recognition
Proceedings of the 11th International Conference on Distributed Smart Cameras, 2017Co-Authors: Emmanuel A Castillo, Ali AhmadiniaAbstract:Smart Cameras brought sight to the idea of cameras as sensors for visual Data rather than strictly for taking pictures. One set of applications that leverages this idea are image recognition applications. Unfortunately, a main drawback on these applications is the hardware limitations that they compromise with due to many of its applications residing in the embedded domain. As a matter of fact, a Deep Convolutional Neural Network (DCNN) is the main general algorithm used in handling the image recognition tasks that can be costly in response time, power consumption and Data Transfer Bandwidth. However, the general architecture of a DCNN is consisted of layers that do specific processing tasks. These distribution of layers can be efficiently organized on a system consisted of Smart Cameras that can improve response time, limit power usage and reduce Data Transfer Bandwidth. A concept is proposed to distribute the layers of a DCNN within a distributed set of Smart Cameras on embedded devices, an edge device and the Cloud that may improve response time, power consumption and Data Transfer Bandwidth.
