The Experts below are selected from a list of 135 Experts worldwide ranked by ideXlab platform
Zeljko Zilic - One of the best experts on this subject based on the ideXlab platform.
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Enabling efficient post-silicon Debug by clustering of hardware-assertions
2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010Co-Authors: M. H. Neishaburi, Zeljko ZilicAbstract:Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon Debugging based on the insertion of hardware checkers in the Debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardware-assertions and controlling each cluster selectively during the Debug Mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient Debug scheduling.
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DATE - Enabling efficient post-silicon Debug by clustering of hardware-assertions
2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010Co-Authors: M. H. Neishaburi, Zeljko ZilicAbstract:Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon Debugging based on the insertion of hardware checkers in the Debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardware-assertions and controlling each cluster selectively during the Debug Mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient Debug scheduling.
M. H. Neishaburi - One of the best experts on this subject based on the ideXlab platform.
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Enabling efficient post-silicon Debug by clustering of hardware-assertions
2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010Co-Authors: M. H. Neishaburi, Zeljko ZilicAbstract:Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon Debugging based on the insertion of hardware checkers in the Debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardware-assertions and controlling each cluster selectively during the Debug Mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient Debug scheduling.
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DATE - Enabling efficient post-silicon Debug by clustering of hardware-assertions
2010 Design Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010Co-Authors: M. H. Neishaburi, Zeljko ZilicAbstract:Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the first silicon becomes available. We consider the Assertion Based Verification techniques for the post-silicon Debugging based on the insertion of hardware checkers in the Debug infrastructure for complex systems on chip. This paper proposes a method to cluster hardware-assertion checkers using the graph partitioning approach. It turns out that having the clusters of hardware-assertions and controlling each cluster selectively during the Debug Mode and normal operation of the circuit makes integration of assertions inside the circuits easier, and causes lower energy consumption and efficient Debug scheduling.
Sascha Uhrig - One of the best experts on this subject based on the ideXlab platform.
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Tracing Static Fields of Embedded Parallel Java Applications
2011 IEEE 35th Annual Computer Software and Applications Conference Workshops, 2011Co-Authors: Sascha UhrigAbstract:Debugging sequential application code is supported by almost any development environment. But newly upcoming parallel systems rise even harder challenges to application Debugging. This is because interrupting or stepping through one of the parallel threads means influencing the concurrent threads. As a result, the system behaves completely different in Debug Mode as in release Mode. This paper presents an approach to identify problems arising from a parallel workload of embedded Java systems. The presented technique is implemented within an embedded Java environment using a multithreaded Java processor.
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COMPSAC Workshops - Tracing Static Fields of Embedded Parallel Java Applications
2011 IEEE 35th Annual Computer Software and Applications Conference Workshops, 2011Co-Authors: Sascha UhrigAbstract:Debugging sequential application code is supported by almost any development environment. But newly upcoming parallel systems rise even harder challenges to application Debugging. This is because interrupting or stepping through one of the parallel threads means influencing the concurrent threads. As a result, the system behaves completely different in Debug Mode as in release Mode. This paper presents an approach to identify problems arising from a parallel workload of embedded Java systems. The presented technique is implemented within an embedded Java environment using a multithreaded Java processor.
Mrugesh Walimbe - One of the best experts on this subject based on the ideXlab platform.
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jtag axi Debug ip with performance meter Mode
Microprocessor Test and Verification, 2014Co-Authors: Mrugesh WalimbeAbstract:The typical multi core SOC of today faces several development constraints. While the process and methodology plans for a first pass silicon, it is not always guaranteed. A true SOC design team always plans for Debug capability when the SOC samples arrive. A Debug/Test solution should also not increase the complexity and schedule of design, verification and physical design process. The Debug/Test solution discussed provides a method to Debug/Test the SOC and at the same time cater towards measuring performance in Debug Mode. This paper is targeted for the IP and SOC design teams developing the Debug architecture in a SOC. It focuses on simplifying the Debug process. It focusses on SOC interconnect performance measurement in Debug Mode. This paper describes a Debug/Test solution which can be used to Debug a SOC. It provides for inbuilt interconnect path performance measurement in absence of processor based control. It also provides for the ability to provide sequencing in the interconnect transactions to simulate real time interconnect activity.
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MTV - JTAG-AXI Debug IP with Performance Meter Mode
2014 15th International Microprocessor Test and Verification Workshop, 2014Co-Authors: Mrugesh WalimbeAbstract:The typical multi core SOC of today faces several development constraints. While the process and methodology plans for a first pass silicon, it is not always guaranteed. A true SOC design team always plans for Debug capability when the SOC samples arrive. A Debug/Test solution should also not increase the complexity and schedule of design, verification and physical design process. The Debug/Test solution discussed provides a method to Debug/Test the SOC and at the same time cater towards measuring performance in Debug Mode. This paper is targeted for the IP and SOC design teams developing the Debug architecture in a SOC. It focuses on simplifying the Debug process. It focusses on SOC interconnect performance measurement in Debug Mode. This paper describes a Debug/Test solution which can be used to Debug a SOC. It provides for inbuilt interconnect path performance measurement in absence of processor based control. It also provides for the ability to provide sequencing in the interconnect transactions to simulate real time interconnect activity.
Roscoe Ainsworth Bartlett - One of the best experts on this subject based on the ideXlab platform.
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Teuchos C++ memory management classes, idioms, and related topics, the complete reference : a comprehensive strategy for safe and efficient memory management in C++ for high performance computing.
2010Co-Authors: Roscoe Ainsworth BartlettAbstract:The ubiquitous use of raw pointers in higher-level code is the primary cause of all memory usage problems and memory leaks in C++ programs. This paper describes what might be considered a radical approach to the problem which is to encapsulate the use of all raw pointers and all raw calls to new and delete in higher-level C++ code. Instead, a set of cooperating template classes developed in the Trilinos package Teuchos are used to encapsulate every use of raw C++ pointers in every use case where it appears in high-level code. Included in the set of memory management classes is the typical reference-counted smart pointer class similar to boost::shared ptr (and therefore C++0x std::shared ptr). However, what is missing in boost and the new standard library are non-reference counted classes for remaining use cases where raw C++ pointers would need to be used. These classes have a Debug build Mode where nearly all programmer errors are caught and gracefully reported at runtime. The default optimized build Mode strips all runtime checks and allows the code to perform as efficiently as raw C++ pointers with reasonable usage. Also included is a novel approach for dealing with the circular references problemmore » that imparts little extra overhead and is almost completely invisible to most of the code (unlike the boost and therefore C++0x approach). Rather than being a radical approach, encapsulating all raw C++ pointers is simply the logical progression of a trend in the C++ development and standards community that started with std::auto ptr and is continued (but not finished) with std::shared ptr in C++0x. Using the Teuchos reference-counted memory management classes allows one to remove unnecessary constraints in the use of objects by removing arbitrary lifetime ordering constraints which are a type of unnecessary coupling [23]. The code one writes with these classes will be more likely to be correct on first writing, will be less likely to contain silent (but deadly) memory usage errors, and will be much more robust to later refactoring and maintenance. The level of Debug-Mode runtime checking provided by the Teuchos memory management classes is stronger in many respects than what is provided by memory checking tools like Valgrind and Purify while being much less expensive. However, tools like Valgrind and Purify perform a number of types of checks (like usage of uninitialized memory) that makes these tools very valuable and therefore complement the Teuchos memory management Debug-Mode runtime checking. The Teuchos memory management classes and idioms largely address the technical issues in resolving the fragile built-in C++ memory management Model (with the exception of circular references which has no easy solution but can be managed as discussed). All that remains is to teach these classes and idioms and expand their usage in C++ codes. The long-term viability of C++ as a usable and productive language depends on it. Otherwise, if C++ is no safer than C, then is the greater complexity of C++ worth what one gets as extra features? Given that C is smaller and easier to learn than C++ and since most programmers don't know object-orientation (or templates or X, Y, and Z features of C++) all that well anyway, then what really are most programmers getting extra out of C++ that would outweigh the extra complexity of C++ over C? C++ zealots will argue this point but the reality is that C++ popularity has peaked and is becoming less popular while the popularity of C has remained fairly stable over the last decade22. Idioms like are advocated in this paper can help to avert this trend but it will require wide community buy-in and a change in the way C++ is taught in order to have the greatest impact. To make these programs more secure, compiler vendors or static analysis tools (e.g. klocwork23) could implement a preprocessor-like language similar to OpenMP24 that would allow the programmer to declare (in comments) that certain blocks of code should be ''pointer-free'' or allow smaller blocks to be 'pointers allowed'. This would significantly improve the robustness of code that uses the memory management classes described here.« less
