The Experts below are selected from a list of 2049 Experts worldwide ranked by ideXlab platform
Sreela Sasi - One of the best experts on this subject based on the ideXlab platform.
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RNS based Programmable Decimation Filter for Multi-Standard Wireless Transceivers 57 RNS based Programmable Decimation Filter for Multi-Standard Wireless Transceivers
2015Co-Authors: Shahana T. K, Babita R. Jose, Rekha K. James, Poulose K. Jacob, Sreela SasiAbstract:Current research on radio frequency transceivers focuses on multi-standard architectures to attain higher system capacities and data rates. Multiple communication standards are made adaptable by per-forming channel select Filtering on chip at baseband in digital domain. The computationally intensive Decimation Filter in a sigma-delta analog-to-digital converter plays an important role in channel selec-tion for multi-mode systems. As these architectures are targeted for portable applications, an area and power efficient reconfigurable implementation is an implicit requirement. To this end, a multi-stage, pro-grammable Decimation Filter based on residue num-ber system (RNS) that is adaptable for WCDMA and WLAN standards is presented in this research. Multi-stage Decimation Filter implementation offers low computational complexity and power dissipation. The FIR Filters of the multi-stage decimator operat-ing in RNS domain offers high data rate because of the carry free operations on smaller residues in par-allel channels. Further power saving is achieved by reconfiguring the hardware architecture, and power-ing down the unused blocks in each mode of opera-tion. For increased programmability modulo multi-plication is performed by index addition utilizing the arithmetic benefits associated with Galois field. Fi-nally, a performance comparison of the proposed RNS based Decimation Filter with traditional binary imple-mentation is done in terms of area, critical path delay and power dissipation
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Decimation Filter Design Toolbox for Multi- Standard Wireless Transceivers using MATLAB
2013Co-Authors: Shahana T. K, Babita R. Jose, Poulose K. Jacob, Sreela SasiAbstract:Abstract—The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. A multi-standard design often involves extensive system level analysis and architectural partitioning, typically requiring extensive calculations. In this research, a Decimation Filter design tool for wireless communication standards consisting of GSM, WCDMA, WLANa, WLANb, WLANg and WiMAX is developed in MATLAB ® using GUIDE environment for visual analysis. The user can select a required wireless communication standard, and obtain the corresponding multistage Decimation Filter implementation using this toolbox. The toolbox helps the user or design engineer to perform a quick design and analysis of Decimation Filter for multiple standards without doing extensive calculation of the underlying methods. toolbox, Multi-Keywords—Decimation Filter, MATLAB ® standard transceivers, Sigma-delta A/D converter. C I
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gui based Decimation Filter design tool for multi standard wireless transceivers
IEEE Conference on Electron Devices and Solid-State Circuits, 2007Co-Authors: T K Shahana, Babita R. Jose, Rekha K. James, Poulose K. Jacob, Sreela SasiAbstract:The demand for new telecommunication services requiring higher capacities, data rates and different operating modes have motivated the development of new generation multi-standard wireless transceivers. A multi-standard design often involves extensive system level analysis and architectural partitioning, typically requiring extensive calculations. To expedite the handling of complicated design calculations, a GUI based design tool is proposed in this paper. In particular, multi-standard Decimation Filter design for six wireless communication standards consisting of GSM, WCDMA, WLANa, WLANb, WLANg and WiMAX is focused. Decimation is done in two or three stages to reduce the hardware complexity and power dissipation. The Decimation Filter design tool is developed using the graphical user interface development environment (GUIDE) in MATLABreg. The implementation complexity in terms of Filter length that meets the specification for any of these standards is computed using this tool and is tabulated.
Habib Mehrez - One of the best experts on this subject based on the ideXlab platform.
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Low power Comb Decimation Filter Using Polyphase Decomposition For Mono-Bit ¢ ¡ Analog-to-Digital Converters Abstract
2008Co-Authors: Yannick Dumonteix, Hassan Aboushady, Habib Mehrez, M. M. LouëratAbstract:A power efficient multirate multistage Comb Decimation Filter for monobit £¥ ¤ A/D converters is presented. Polyphase decomposition in all stages with high Decimation factor in the first stage, are used to reduce the frequency of the input signal. Several implementations have shown that proper choice of the Decimation factor of the first stage can reduce power consumption by more than 30 % The multistage architecture makes the total Decimation factor easily programmable and suitabale for multi-standard applications.
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efficient polyphase decomposition of comb Decimation Filters in spl sigma spl utri analog to digital converters
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 2001Co-Authors: Hassan Aboushady, Yannick Dumonteix, M. M. Louërat, Habib MehrezAbstract:A power efficient multirate multistage Comb Decimation Filter for mono-bit and multi-bit /spl Sigma//spl utri/ A/D converters is presented. Polyphase decomposition in all stages, with high Decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb Filter. Several implementations indicate that proper choice of the first stage Decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit /spl Sigma//spl utri/ A/Ds, this optimum first stage Decimation factor is a function of the input wordlength.
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Low-power Comb Decimation Filter Using Polyphase Decomposition For Mono-bit Sigma-Delta Analog-to-Digital Converters
2000Co-Authors: Yannick Dumonteix, Hassan Aboushady, Habib Mehrez, Marie-minerve Rosset-louëratAbstract:A power efficient multirate multistage Comb Decimation Filter for monobit Σ∆ A/D converters is presented. Polyphase decomposition in all stages with high Decimation factor in the first stage, are used to reduce the frequency of the input signal. Several implementations have shown that proper choice of the Decimation factor of the first stage can reduce power consumption by more than 30% The multistage architecture makes the total Decimation factor easily programmable and suitabale for multi-standard applications.
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efficient polyphase decomposition of comb Decimation Filters in spl sigma spl delta analog to digital converters
Midwest Symposium on Circuits and Systems, 2000Co-Authors: Hassan Aboushady, Yannick Dumonteix, M. M. Louërat, Habib MehrezAbstract:A power efficient multi-rate multi-stage Comb Decimation Filter for mono-bit and multi-bit /spl Sigma//spl Delta/ A/D converters is presented. Polyphase decomposition in all stages, with high Decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb Filter. Several implementations indicate that proper choice of the first stage Decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit /spl Sigma//spl Delta/ A/Ds, this optimum first stage Decimation factor is function of the input wordlength.
J Wetherrell - One of the best experts on this subject based on the ideXlab platform.
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a compact low power Decimation Filter for sigma delta modulators
International Conference on Acoustics Speech and Signal Processing, 2000Co-Authors: J WetherrellAbstract:Sigma delta modulators can provide the lowest power and area solution for high resolution A/D converters. Unfortunately the required Decimation Filter for the modulator tends to consume much more power and area than the modulator. This paper solves both problem by introducing a new FIR-Sinc architecture and taking advantage of the low number of bits at the input. Careful choice of pipelining and logic style and the use of multiple-V/sub DD/ logic lead to a low power implementation without compromising on performance and area. The power consumed is 93% less and area used is 14% less than the best reported designs. The 64-tap programmable Decimation Filter with 10-bit coefficients consumes 1.5 mW of power and 0.71 mm/sup 2/ of area running on a 40 MHz 1.5 bit input with a 1.25 MHz 15 bit output on a 1.65 V supply.
K. Grati - One of the best experts on this subject based on the ideXlab platform.
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on design and implementation of a Decimation Filter for multistandard wireless transceivers
IEEE Transactions on Wireless Communications, 2002Co-Authors: A. Ghazel, Lirida Alves De Barros Naviner, K. GratiAbstract:In this work, we deal with the design and implementation of a Decimation Filter to be used in wideband radio-frequency receiver. The paper outlines architecture considerations for multistandard wireless transceivers. Also, it describes the design steps and the tradeoffs concerning the hardware implementation. GSM and DECT standards specifications are met by the proposed Filtering cascade structure. The Filter processes six-bit data stream input from a fourth-order sigma-delta modulator and has been prototyped in a field-programmable gate array device.
Hassan Aboushady - One of the best experts on this subject based on the ideXlab platform.
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Low power Comb Decimation Filter Using Polyphase Decomposition For Mono-Bit ¢ ¡ Analog-to-Digital Converters Abstract
2008Co-Authors: Yannick Dumonteix, Hassan Aboushady, Habib Mehrez, M. M. LouëratAbstract:A power efficient multirate multistage Comb Decimation Filter for monobit £¥ ¤ A/D converters is presented. Polyphase decomposition in all stages with high Decimation factor in the first stage, are used to reduce the frequency of the input signal. Several implementations have shown that proper choice of the Decimation factor of the first stage can reduce power consumption by more than 30 % The multistage architecture makes the total Decimation factor easily programmable and suitabale for multi-standard applications.
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efficient polyphase decomposition of comb Decimation Filters in spl sigma spl utri analog to digital converters
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 2001Co-Authors: Hassan Aboushady, Yannick Dumonteix, M. M. Louërat, Habib MehrezAbstract:A power efficient multirate multistage Comb Decimation Filter for mono-bit and multi-bit /spl Sigma//spl utri/ A/D converters is presented. Polyphase decomposition in all stages, with high Decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb Filter. Several implementations indicate that proper choice of the first stage Decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit /spl Sigma//spl utri/ A/Ds, this optimum first stage Decimation factor is a function of the input wordlength.
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Low-power Comb Decimation Filter Using Polyphase Decomposition For Mono-bit Sigma-Delta Analog-to-Digital Converters
2000Co-Authors: Yannick Dumonteix, Hassan Aboushady, Habib Mehrez, Marie-minerve Rosset-louëratAbstract:A power efficient multirate multistage Comb Decimation Filter for monobit Σ∆ A/D converters is presented. Polyphase decomposition in all stages with high Decimation factor in the first stage, are used to reduce the frequency of the input signal. Several implementations have shown that proper choice of the Decimation factor of the first stage can reduce power consumption by more than 30% The multistage architecture makes the total Decimation factor easily programmable and suitabale for multi-standard applications.
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efficient polyphase decomposition of comb Decimation Filters in spl sigma spl delta analog to digital converters
Midwest Symposium on Circuits and Systems, 2000Co-Authors: Hassan Aboushady, Yannick Dumonteix, M. M. Louërat, Habib MehrezAbstract:A power efficient multi-rate multi-stage Comb Decimation Filter for mono-bit and multi-bit /spl Sigma//spl Delta/ A/D converters is presented. Polyphase decomposition in all stages, with high Decimation factor in the first stage, is used to significantly reduce the sampling frequency of the Comb Filter. Several implementations indicate that proper choice of the first stage Decimation factor can considerably improve power consumption, area and maximum sampling frequency. In multibit /spl Sigma//spl Delta/ A/Ds, this optimum first stage Decimation factor is function of the input wordlength.
