The Experts below are selected from a list of 27126 Experts worldwide ranked by ideXlab platform
K Nakazawa - One of the best experts on this subject based on the ideXlab platform.
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analog recurrent Decision Circuit with high signal voltage symmetry and delay time equality to improve continuous time convergence performance
IEEE Transactions on Neural Networks, 2003Co-Authors: Akira Hirose, K NakazawaAbstract:This paper reports experimental results showing that the recall dynamics of analog associative memories is largely influenced by signal-voltage symmetry of synaptic weights and inverse-noninverse delay-time equality of neurons. We propose a highly symmetric synapse and an equi-delaying neuron. We fabricated an association chip comprised of them to demonstrate a high association performance. In comparison experiments, we also observe large performance degradations when the symmetry or delay equality is deteriorated. We analyze the dynamics based on the statistics of recall results. The proposals and the analysis results are widely applicable to analog recurrent convergence Circuits.
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analog continuous time recurrent Decision Circuit with high signal voltage symmetry and delay time equality
International Symposium on Circuits and Systems, 2003Co-Authors: Akira Hirose, K NakazawaAbstract:Recurrent-convergence Decision Circuits include the historic Hopfield neural networks as well as prospective turbo decoders. For these applications, we propose two novel Circuit elements: (1) a quick-response synaptic weight with high symmetry in both small-signal and large-amplitude operations and (2) an open-loop, quick-response and symmetrically parallel neuron Circuit that has inverse and non-inverse outputs with delay-time equality and high signal-amplitude symmetry. We report the characteristics of these elements in a fabricated associative memory chip. We also analyze how the recalling statistics depend on the variation of the symmetry and delay equality of the elements. It is demonstrated that the proposals are very effective to improve the neural association performance.
J Godin - One of the best experts on this subject based on the ideXlab platform.
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high sensitivity inp ingaas dhbt Decision Circuit design and application in optical and system experiments at 40 43 gbit s
IEEE Transactions on Microwave Theory and Techniques, 2005Co-Authors: A Konczykowska, F Jorge, W Idler, J GodinAbstract:A high-input-sensitivity Decision D flip-flop integrated Circuit was designed and fabricated in a self-aligned InP double heterojunction bipolar transistor technology (F/sub t/=180 GHz, F/sub max/=220 GHz). Circuit measurements at 40 Gbit/s show excellent eye quality, 15-mV sensitivity, and good clock phase margin. Two optical experiments, i.e., assessment of Decision Circuit reamplifying, reshaping, and retiming capabilities in 40-Gbit/s nonreturn-to-zero (full rate) photoreceiver and 43-Gbit/s optical signal noise ratio measurement (21.8 dB/0.1 nm for 10/sup -9/ BER) are also presented.
K Murata - One of the best experts on this subject based on the ideXlab platform.
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43 gbit s 200 km unrepeatered transmission experiment using high sensitivity digital oeic receiver module
Electronics Letters, 2002Co-Authors: Shoichiro Kuwahara, Kazushige Yonenaga, Y Miyamoto, K Murata, N Kitabayashi, Nobuo Shimizu, H TobaAbstract:The first transmission results using a monolithic digital optoelectronic integrated Circuit (OEIC), which consists of a uni-travelling-carrier photodiode and an InP high electron mobility transistor Decision Circuit, are presented. High receiver sensitivity of -30.2 dBm was obtained at the bit rate of 43 Gbit/s with 150 km dispersion-shifted fibre transmission. It is confirmed that the transmission distance can be extended to over 200 km by employing forward error correction code.
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43 gbit s 200 km unrepeatered transmission experiment using high sensitivity digital oeic receiver module
Electronics Letters, 2002Co-Authors: Shoichiro Kuwahara, Kazushige Yonenaga, Y Miyamoto, K Murata, N Kitabayashi, Nobuo Shimizu, H TobaAbstract:The first transmission results using a monolithic digital optoelectronic integrated Circuit (OEIC), which consists of a uni-travelling-carrier photodiode and an InP high electron mobility transistor Decision Circuit, are presented. High receiver sensitivity of −30.2 dBm was obtained at the bit rate of 43 Gbit/s with 150 km dispersion-shifted fibre transmission. It is confirmed that the transmission distance can be extended to over 200 km by employing forward error correction code.
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a novel high speed latching operation flip flop hlo ff Circuit and its application to a 19 gb s Decision Circuit using a 0 2 spl mu m gaas mesfet
IEEE Journal of Solid-state Circuits, 1995Co-Authors: K Murata, E Sano, Taiichi Otsuji, M Ohhata, M Togashi, M SuzukiAbstract:This paper describes a novel high-speed flip-flop Circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two Decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF Decision Circuit at 19 Gb/s. >
S P Voinigescu - One of the best experts on this subject based on the ideXlab platform.
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a 40 gb s Decision Circuit in 90 nm cmos
European Solid-State Circuits Conference, 2006Co-Authors: T Chalvatzis, K H K Yau, Peter Schvan, M T Yang, S P VoinigescuAbstract:A low-power 40-Gb/s Decision Circuit for fiber-optic and mm-wave analog-to-digital converter applications was implemented in two 90-nm processes from two different foundries. The Circuit uses a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. It combines low and high-VT MOSFETs to allow for operation from a 1.2-V supply, without compromising speed. Full-rate retiming with jitter reduction and 7 ps rise/fall times is demonstrated at 37 Gb/s and 40 Gb/s from 1.2 V and 1.5 V, respectively. The entire Decision Circuit dissipates 130 mW from 1.2 V, with a record low power consumption of 10.8 mW per latch.
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a 2 5 v 45 gb s Decision Circuit using sige bicmos logic
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Timothy O Dickson, R Beerkens, S P VoinigescuAbstract:A 45-Gb/s BiCMOS Decision Circuit operating from a 2.5-V supply is reported. The full-rate retiming flip-flop operates from the lowest supply voltage of any silicon-based flip-flop demonstrated to date at this speed. MOS and SiGe heterojunction-bipolar-transistor (HBT) current-mode logic families are compared. Capitalizing on the best features of both families, a true BiCMOS logic topology is presented that allows for operation from lower supply voltages than pure HBT implementations without compromising speed. The topology, based on a BiCMOS cascode, can also be applied to a number of millimeter-wave (mm-wave) Circuits. In addition to the retiming flip-flop, the Decision Circuit includes a broadband transimpedance preamplifier to improve sensitivity, a tuned 45-GHz clock buffer, and a 50-/spl Omega/ output driver. The first mm-wave transformer is employed along the clock path to perform single-ended-to-differential conversion. The entire Circuit, which is implemented in a production 130-nm BiCMOS process with 150-GHz f/sub T/ SiGe HBT, consumes 288 mW from a 2.5-V supply, including only 58 mW from the flip-flop.
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a 2 5 v 40 gb s Decision Circuit using sige bicmos logic
Symposium on VLSI Circuits, 2004Co-Authors: Timothy O Dickson, R Beerkens, S P VoinigescuAbstract:A 40-Gb/s Decision Circuit is reported which operates from a 2.5-V supply. It includes a flip-flop, a broadband transimpeclance preamplifier, a tuned 40-GHz clock buffer, and a 50-/spl Omega/ output driver. The flipflop features a novel BiCMOS CML logic topology, which allows for lower supply voltages as compared with pure bipolar implementations without compromising speed. A mm-wave transformer is used to perform single-ended-to-differential conversion along the 40 GHz clock path.
Akira Hirose - One of the best experts on this subject based on the ideXlab platform.
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analog recurrent Decision Circuit with high signal voltage symmetry and delay time equality to improve continuous time convergence performance
IEEE Transactions on Neural Networks, 2003Co-Authors: Akira Hirose, K NakazawaAbstract:This paper reports experimental results showing that the recall dynamics of analog associative memories is largely influenced by signal-voltage symmetry of synaptic weights and inverse-noninverse delay-time equality of neurons. We propose a highly symmetric synapse and an equi-delaying neuron. We fabricated an association chip comprised of them to demonstrate a high association performance. In comparison experiments, we also observe large performance degradations when the symmetry or delay equality is deteriorated. We analyze the dynamics based on the statistics of recall results. The proposals and the analysis results are widely applicable to analog recurrent convergence Circuits.
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analog continuous time recurrent Decision Circuit with high signal voltage symmetry and delay time equality
International Symposium on Circuits and Systems, 2003Co-Authors: Akira Hirose, K NakazawaAbstract:Recurrent-convergence Decision Circuits include the historic Hopfield neural networks as well as prospective turbo decoders. For these applications, we propose two novel Circuit elements: (1) a quick-response synaptic weight with high symmetry in both small-signal and large-amplitude operations and (2) an open-loop, quick-response and symmetrically parallel neuron Circuit that has inverse and non-inverse outputs with delay-time equality and high signal-amplitude symmetry. We report the characteristics of these elements in a fabricated associative memory chip. We also analyze how the recalling statistics depend on the variation of the symmetry and delay equality of the elements. It is demonstrated that the proposals are very effective to improve the neural association performance.
