The Experts below are selected from a list of 475839 Experts worldwide ranked by ideXlab platform
I M Sokolov - One of the best experts on this subject based on the ideXlab platform.
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influence of adhesion of silica and ceria abrasive nanoparticles on chemical mechanical planarization of silica surfaces
Applied Surface Science, 2011Co-Authors: Dmytro Volkov, P Veera R Dandu, H Goodman, B Santora, I M SokolovAbstract:Abstract We report on a direct measurement of adhesion between abrasive nanoparticles of irregular shape, which are used in semiconductor industry in the process of Chemical–Mechanical Planarization (CMP), and silica surface. The adhesion of ceria and silica nanoparticles to silica surface is measured in multiple chemistries of different CMP slurries using a specially developed atomic force microscopy (AFM) method. Using this method, we study the influence of adhesion on the main parameters of CMP, removal rate and Defectivity, scratches. While being plausible to expect correlation between these parameters and adhesion, it has not been systematically studied as of yet. We observed direct correlation between adhesion and removal rate. Comparing the measured Defectivity and adhesion, we observe the presence of some correlation between these parameters. We conclude that both adhesion and shape of abrasive particles influence Defectivity, micro-scratches. Direct measurements of the adhesion between abrasive nano-particles and surface can be used in the screening of new slurries as well as various modeling related to wearing of the surfaces.
Soidri Bastoini - One of the best experts on this subject based on the ideXlab platform.
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Optimisation of the process control in a semiconductor company: model and case study of Defectivity sampling
International Journal of Production Research, 2011Co-Authors: M'hammed Sahnoun, Samuel Bassetto, Michel Tollenaere, Philippe Vialletelle, Soidri BastoiniAbstract:This article studies the skip, under some assumptions, of process control operations. The case of one tool, one enhanced buffer and one metrology tool of a monotonic parameter is analysed. This article presents circumstances in which control plan can be optimised due to the buffer's behaviour. After discussing the industrial issue of Defectivity, this article presents a literature review followed by the model and steps towards industrial development. Then demonstrator, which is applied at a case study of Defectivity sampling, is presented. A test of over a 300-mm wafer fabrication data set shows serious improvements - around 35% of Defectivity controls have been skipped compared to the static sampling plan.
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Computation of Wafer-At-Risk from Theory to Real Life Demonstration
2010Co-Authors: M'hammed Sahnoun, Samuel Bassetto, Michel Tollenaere, Philippe Vialletelle, Soidri BastoiniAbstract:Over the past decade, control of process tools has progressively moved from bare non-product wafers inspection toward on-product measurements. Nevertheless, in high-mix facilities, recipe creation for all products is not possible. Most of the semiconductor fabs use today "high runners" lots that are flagged for Defectivity. Due to non-linearity and variability of the line [1], lots may be stopped, overtake each-other or ignore certain tools. This is the drawback of this sampling method: the efficiency of the Defectivity measurement with respect to information is often under optimal. On an other hand, the measurement equipments are very expensive and fabs are limited in capacity of inspection. Using the sampling method already quoted, we take the risk of controlling some lots unnecessarily. The aim of this study is to evaluate this risk and to propose a solution to optimize the use of control equipment. The case study described here takes place in STMicroelectronics 300mm wafer fab in Crolles, France. It considers the global fab toolset and studies the skip, under some assumptions, of a Defectivity measurement. The Wafer-At-Risk is in use as the risk evaluation of each tool. The information brought by each lot that can be inspected is called the Wafer-At-Risk-Reduction. The problem is that this data is not directly available in fab, so, an algorithm was developed for the computation of the Wafer-At-Risk and Wafer-At-Risk-Reduction.
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Optimization of the process control in a semiconductor company. Model and case study of Defectivity sampling
International Journal of Production Research, 2010Co-Authors: M'hammed Sahnoun, Samuel Bassetto, Soidri Bastoini, Philippe VialetelleAbstract:This paper studies the skip, under some assumptions, of process control operations. The case of one tool, one enhanced buffer and one metrology tool of a monotonic parameter is analyzed. The paper presents circumstances in which control plan can be optimized due to buffer behavior's. After presenting the industrial issue of Defectivity, the article goes through literature review. The article follows by presenting the model and steps toward industrial development. A demonstrator is then presented applied at a case study of Defectivity sampling. A test over a 300mm wafer-fab data set shows serious improvements: around 35% of Defectivity controls have been allowed to be skipped compared to the static sampling plan.
M'hammed Sahnoun - One of the best experts on this subject based on the ideXlab platform.
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Optimisation of the process control in a semiconductor company: model and case study of Defectivity sampling
International Journal of Production Research, 2011Co-Authors: M'hammed Sahnoun, Samuel Bassetto, Michel Tollenaere, Philippe Vialletelle, Soidri BastoiniAbstract:This article studies the skip, under some assumptions, of process control operations. The case of one tool, one enhanced buffer and one metrology tool of a monotonic parameter is analysed. This article presents circumstances in which control plan can be optimised due to the buffer's behaviour. After discussing the industrial issue of Defectivity, this article presents a literature review followed by the model and steps towards industrial development. Then demonstrator, which is applied at a case study of Defectivity sampling, is presented. A test of over a 300-mm wafer fabrication data set shows serious improvements - around 35% of Defectivity controls have been skipped compared to the static sampling plan.
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Computation of Wafer-At-Risk from Theory to Real Life Demonstration
2010Co-Authors: M'hammed Sahnoun, Samuel Bassetto, Michel Tollenaere, Philippe Vialletelle, Soidri BastoiniAbstract:Over the past decade, control of process tools has progressively moved from bare non-product wafers inspection toward on-product measurements. Nevertheless, in high-mix facilities, recipe creation for all products is not possible. Most of the semiconductor fabs use today "high runners" lots that are flagged for Defectivity. Due to non-linearity and variability of the line [1], lots may be stopped, overtake each-other or ignore certain tools. This is the drawback of this sampling method: the efficiency of the Defectivity measurement with respect to information is often under optimal. On an other hand, the measurement equipments are very expensive and fabs are limited in capacity of inspection. Using the sampling method already quoted, we take the risk of controlling some lots unnecessarily. The aim of this study is to evaluate this risk and to propose a solution to optimize the use of control equipment. The case study described here takes place in STMicroelectronics 300mm wafer fab in Crolles, France. It considers the global fab toolset and studies the skip, under some assumptions, of a Defectivity measurement. The Wafer-At-Risk is in use as the risk evaluation of each tool. The information brought by each lot that can be inspected is called the Wafer-At-Risk-Reduction. The problem is that this data is not directly available in fab, so, an algorithm was developed for the computation of the Wafer-At-Risk and Wafer-At-Risk-Reduction.
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Optimization of the process control in a semiconductor company. Model and case study of Defectivity sampling
International Journal of Production Research, 2010Co-Authors: M'hammed Sahnoun, Samuel Bassetto, Soidri Bastoini, Philippe VialetelleAbstract:This paper studies the skip, under some assumptions, of process control operations. The case of one tool, one enhanced buffer and one metrology tool of a monotonic parameter is analyzed. The paper presents circumstances in which control plan can be optimized due to buffer behavior's. After presenting the industrial issue of Defectivity, the article goes through literature review. The article follows by presenting the model and steps toward industrial development. A demonstrator is then presented applied at a case study of Defectivity sampling. A test over a 300mm wafer-fab data set shows serious improvements: around 35% of Defectivity controls have been allowed to be skipped compared to the static sampling plan.
Jacques Pinaton - One of the best experts on this subject based on the ideXlab platform.
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Dispatching of Lots to Dynamically Reduce the Wafers at Risk in Semiconductor Manufacturing
2012Co-Authors: Gloria Luz Rodriguez Verjan, Eric Tartiere, Jacques Pinaton, Stéphane Dauzère-pérès, Alexis ThieullenAbstract:This paper presents a lot dispatching strategy to reduce the Wafer at Risk (W@R) on process tools, i.e. the number of wafers processed between two Defectivity inspections. Due to the highly complex manufacturing process and the molecular scope of operations, Defectivity inspections are critical for sustaining high yield levels of products. The novel dispatching strategy guides operators in selecting lots that will later be controlled in Defectivity. Results show that the system is effective since the impact of measures has improved and the Wafer at Risk on process tools has been reduced
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IMPACT OF CONTROL PLAN DESIGN ON TOOL RISK MANAGEMENT: A SIMULATION STUDY IN SEMICONDUCTOR MANUFACTURING
Winter Simulation Conference, 2011Co-Authors: Gloria Luz Rodriguez Verjan, Stéphane Dauzère-pérès, Jacques PinatonAbstract:In this paper, we analyze the impact of control plan design of Defectivity inspections for tool risk management. Defectivity inspections are performed on products and can reveal the yield loss produced by contaminations or structural flaws. The risk considered in this paper concerns the exposure level of wafers on a tool between two Defectivity controls. Our goal is to analyze how control plans can impact the manufacturing robustness from the point of view of wafer at risk on tools. A smart sampling strategy is considered for sampling lots to be measured. Actual data from the Rousset fab of STMicroelectronics are used. The simulation experiments are performed using the S5 Simulator developed by EMSE-CMP. Results show that not only the number and positions of controls operations have an important impact on tool risk management, but also how each control operation covers process operations
Katsushi Nakano - One of the best experts on this subject based on the ideXlab platform.
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Topcoat-less resist approach for high volume production and yield enhancement of immersion lithography
Proceedings of SPIE, 2010Co-Authors: Katsushi Nakano, Rei Seki, Toshiyuki Sekito, Tomoharu Fujiwara, Tadamasa Kawakubo, Yoshihiro Maruta, Kenichi Shiraishi, Toshihiko Sei, Tsunehito Hayashi, Yasuhiro IriuchijimaAbstract:Double patterning (DP) is the first candidate for extension of ArF immersion lithography, and topcoat-less (TC-less) process is an attractive process candidate compared to a topcoat process because it can make DP process simpler and reduce the chip manufacturing cost. To make the DP process viable, TC-less process performance including Defectivity, auto focus (AF) and overlay performance must be validated. Nikon's latest volume production immersion lithography tool (S620D), was used for TC-less process evaluation. While S620D shows good Defectivity results with both topcoat and TC-less process at 700mm/s scan speed, TC-less process showed slight improvement in Defectivity compared to topcoat process. One reason being that TC-less process can suppress topcoat originated defect such as topcoat blister. The second reason is that TC-less resist can attain higher hydrophobicity than topcoat. Higher hydrophobicity is advantageous for high speed scanning because of stable movement of water meniscus, resulting in better Defectivity performance. Defectivity results showed clear correlation to dynamic receding contact angle (D-RCA). Blob defect reduction is one of the challenges with TC-less resist process, because hydrophobic surface repels rinse water applied during development rinse process hence generating blob defect. However, the recent material improvements of TC-less resist have overcome this challenge and showed excellent blob defect performance. The hydrophobicity control during development process is the key factor in defect reduction. Wafer edge process is also very important for immersion lithography. The preferable wafer edge treatment for both TCless and topcoat process is to maintain uniform hydrophobicity over the entire wafer including wafer edge. While topcoat can be removed perfectly by development, unexposed TC-less resist remains on the wafer edge. WEE (wafer edge exposure) process can remove the excess resist after exposure, it's effectiveness was confirmed through experimental results. AF and overlay repeatability was evaluated on both topcoat and TC-less process; similar and sufficient performance was obtained on both processes. Based on cost of ownership calculations it is believed a 30% material cost and 10% track hardware cost reduction is feasible. These evaluations provide convincing evidence that TC-less process is ready for 32nm generation and beyond.
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Control and reduction of immersion Defectivity for yield enhancement at high volume production
Proceedings of SPIE, 2009Co-Authors: Katsushi Nakano, Rei Seki, Toshiyuki Sekito, Masato Yoshida, Tomoharu Fujiwara, Yasuhiro Iriuchijima, Soichi OwaAbstract:Volume device manufacturing using immersion lithography is widely accepted as the solution for patterning IC features below 40 nm half pitch. In order to ensure high yield and steady productivity tight control of Defectivity is essential. A major source of defects and tool contamination is the particles introduced by incoming wafers. Particles can be categorized in two groups: particles attached to wafer surface or residues on the wafer edge. Surface or edge peeling of topcoats can also be a source of particle. Adhesion force between topcoat or topcoat-less (TC-less) resist and wafer is one of the most important parameter for particle reduction. Peeling test results proved that TC-less resist has better adhesion performance than topcoat. One of the most commonly used adhesion promoting material is hexamethyldisilazane (HMDS). Application condition of this material is an important factor in preventing wafer edge and surface topcoat peeling. Studies have shown lower temperature and longer application of HMDS shows better adhesion result. Maintaining a clean wafer surface is also a very important factor for particle reduction. Pre-rinse, which can rinse off particles before exposure, was evaluated and the efficiency was confirmed. Edge particles are more effectively reduced by pre-rinse, because weakly attached topcoat and wafer edge residues were effectively removed by pre-rinse. For further particle reduction, edge residue reduction and cut line roughness improvement were evaluated and their effectiveness was confirmed. Lower cut position achieved improved particle counts on both topcoat and TC-less resist; more frequent contact between water and cut-line can weaken the adhesion and consequently peel off topcoat or TC-less resist. Finally the relationship between Defectivity and hydrophobicity is analyzed, high Receding Contact Angle (RCA) showed better Defectivity result. Topcoat and TC-less process is compared for each Defectivity reduction methodology and for each category TC-less process always showed lower Defectivity level and less sensitivity to process conditions, indicating that TC-less process is safer and more robust than topcoat process.
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immersion Defectivity study with volume production immersion lithography tool for 45 nm node and below
Proceedings of SPIE, 2008Co-Authors: Katsushi Nakano, Masato Yoshida, Tomoharu Fujiwara, Yasuhiro Iriuchijima, Kenichi Shiraishi, Shiro Nagaoka, Soichi OwaAbstract:Volume production of 45nm node devices utilizing Nikon's S610C immersion lithography tool has started. Important to the success in achieving high-yields in volume production with immersion lithography has been Defectivity reduction. In this study we evaluate several methods of Defectivity reduction. The tools used in our Defectivity analysis included a dedicated immersion cluster tools consisting of a Nikon S610C, a volume production immersion exposure tool with NA of 1.3, and a resist coater-developer LITHIUS i+ from TEL. In our initial procedure we evaluated Defectivity behavior by comparing on a topcoat-less resist process to a conventional topcoat process. Because of its simplicity the topcoatless resist shows lower defect levels than the topcoat process. In a second study we evaluated the defect reduction by introducing the TEL bevel rinse and pre-immersion bevel cleaning techniques. This technique was shown to successfully reduce the defect levels by reducing the particles at the wafer bevel region. For the third defect reduction method, two types of tool cleaning processes are shown. Finally, we discuss the overall Defectivity behavior at the 45nm node. To facilitate an understanding of the root cause of the defects, defect source analysis (DSA) was applied to separate the defects into three classes according to the source of defects. DSA analysis revealed that more than 99% of defects relate to material and process, and less than 1% of the defects relate to the exposure tool. Material and process optimization by collaborative work between exposure tool vendors, track vendors and material vendors is a key for success of 45nm node device manufacturing.
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Immersion Defectivity control by optimizing immersion materials and processes
Proceedings of SPIE, 2007Co-Authors: Katsushi Nakano, Hiroshi KatoAbstract:Volume production of 55nm node device using Nikon immersion lithography tool, S609B, has started. One very important issue for volume production immersion lithography is Defectivity control. The mainstream resist process for the initial stage of immersion is to use a topcoat, because chip manufacturers can continue to use conventional resist whose lithographic properties are well characterized. On the other hand, because of its simplicity and cost effectiveness, a topcoat-less resist process is an attractive candidate for the second stage of immersion lithography. Intensive study and development of topcoat-less resist is being done by resist vendors. One unexpected benefit of topcoat-less resist is it is much easier to increase hydrophobicity than developer soluble topcoat. For Defectivity analysis of both topcoat and topcoat-less process, a dedicated immersion cluster comprised of a volume production immersion exposure tool, S609B, with NA of 1.07 and a resist coater-developer LITHIUS i+ (TEL) is used. Excellent Defectivity data obtained using various materials and processes are shown in this paper. Understanding the root cause of defects is very important to control them. Defect source analysis (DSA) revealed particles cause many types of defects. Interesting correlations between particles and other topcoat defects and resultant pattern defects are shown in this paper. In the immersion resist process, wafer edge condition is one key issue. Using topcoat-less resist, wafer edge condition and its Defectivity dependency is discussed and analyzed.
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analysis and improvement of Defectivity in immersion lithography
Proceedings of SPIE the International Society for Optical Engineering, 2006Co-Authors: Katsushi Nakano, Soichi Owa, Irfan Malik, Tetsuya Yamamoto, Somnath NagAbstract:In this paper, we report results of comprehensive studies of defects originating in immersion photolithography clusters comprising immersion volume production tool (S609B, NA=1.07) and engineering evaluation tool (EET, NA=0.85). Defectivity of S609B was very low, 0.013 /cm2; it attained dry exposure level successfully. Defectivity results using EET were also very promising in all three major resist processes including solvent soluble topcoat, developer soluble topcoat and topcoat-less resist. Defectivity did not show any scan speed dependency and target size dependency, showing the extendibility of our immersion technology to future mass production phase. In particular, we found that for 50 ml water droplets, receding angle larger than about 70 degree provides immersion process free of immersion-specific defects. We successfully demonstrated very effective defect analysis technique named DSA (defect source analysis) to show what defects are immersion-specific. We also revealed the defect generation mechanism of each defect types. Deep understanding of Defectivity behavior leads to a conclusion that immersion lithography is viable for IC manufacture at 45 nm node.
