The Experts below are selected from a list of 2031 Experts worldwide ranked by ideXlab platform
Adam T. Arnesen - One of the best experts on this subject based on the ideXlab platform.
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Increasing Design Productivity for FPGAs Through IP Reuse and Meta-Data Encapsulation
2014Co-Authors: Adam T. ArnesenAbstract:Increasing Design Productivity for FPGAs Through Intellectual Property Reuse and Meta-Data Encapsulation
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Meta-Data and Interface Synthesis Techniques for Improving Design Productivity in Reconfigurable Computing
2013Co-Authors: Adam T. Arnesen, Michael WirthlinAbstract:This paper demonstrates improvements in Design Productivity for reconfigurable computing which are accomplished through a novel IP reuse strategy. It presents a set of extensions to the IP-XACT XML specification that define the temporal behavior of cores and describes how these extensions are used in the Ogre synthesis system to simplify Design complexity and thereby reduce Design time. Design Productivity improvement is demonstrated by reducing Design time for software radio Designs from days to hours.
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FPL - Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
2010 International Conference on Field Programmable Logic and Applications, 2010Co-Authors: Adam T. Arnesen, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, Kevin Ellsworth, Michael WirthlinAbstract:This paper presents a novel IP core reuse strategy which reduces Design time from days to hours for communication circuits such as digital radio receivers. This Design Productivity is obtained by leveraging a highly parameterized library of communication specific cores. These cores are described in IP-XACT XML with vendor extensions describing the timing behavior of their communication interfaces. A synthesis tool, called Ogre, was created that generates the communication interfaces between cores described in IP-XACT and synthesizes full Designs from structural synchronous dataflow specifications. Design Productivity improvements are demonstrated with several radio receiver Designs.
Michael Wirthlin - One of the best experts on this subject based on the ideXlab platform.
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Meta-Data and Interface Synthesis Techniques for Improving Design Productivity in Reconfigurable Computing
2013Co-Authors: Adam T. Arnesen, Michael WirthlinAbstract:This paper demonstrates improvements in Design Productivity for reconfigurable computing which are accomplished through a novel IP reuse strategy. It presents a set of extensions to the IP-XACT XML specification that define the temporal behavior of cores and describes how these extensions are used in the Ogre synthesis system to simplify Design complexity and thereby reduce Design time. Design Productivity improvement is demonstrated by reducing Design time for software radio Designs from days to hours.
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FPL - Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
2010 International Conference on Field Programmable Logic and Applications, 2010Co-Authors: Adam T. Arnesen, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, Kevin Ellsworth, Michael WirthlinAbstract:This paper presents a novel IP core reuse strategy which reduces Design time from days to hours for communication circuits such as digital radio receivers. This Design Productivity is obtained by leveraging a highly parameterized library of communication specific cores. These cores are described in IP-XACT XML with vendor extensions describing the timing behavior of their communication interfaces. A synthesis tool, called Ogre, was created that generates the communication interfaces between cores described in IP-XACT and synthesizes full Designs from structural synchronous dataflow specifications. Design Productivity improvements are demonstrated with several radio receiver Designs.
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Increasing Design Productivity through core reuse, meta-data encapsulation, and synthesis
Proceedings - 2010 International Conference on Field Programmable Logic and Applications FPL 2010, 2010Co-Authors: Adam Arnesen, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, Kevin Ellsworth, Michael WirthlinAbstract:This paper presents a novel IP core reuse strategy which reduces Design time from days to hours for communication circuits such as digital radio receivers. This Design Productivity is obtained by leveraging a highly parameterized library of communication specific cores. These cores are described in IP-XACT XML with vendor extensions describing the timing behavior of their communication interfaces. A synthesis tool, called Ogre, was created that generates the communication interfaces between cores described in IP-XACT and synthesizes full Designs from structural synchronous dataflow specifications. Design Productivity improvements are demonstrated with several radio receiver Designs.
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Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows
2008Co-Authors: Michael Wirthlin, Brent Nelson, Brad Hutchings, Peter Athanas, Shawn A. BohnerAbstract:Abstract : Interest is growing in the use of FPGA devices for high-performance, efficient parallel computation. The large amount of programmable logic, internal routing, and memory can be used to perform a wide variety of high-performance computation more efficiently than traditional microprocessor-based computing architectures. The Productivity of FPGA Design, however, is very low. FPGA Design is very time consuming and requires low-level hardware Design skills. This study investigated this FPGA Design Productivity problem and identified potential solutions that will provide revolutionary improvements in Design Productivity. Three research areas that must be addressed to achieve such improvements are significant improvement in reuse of FPGA circuits, identification and deployment of higher level Design abstractions, and increasing the number of turns per day to significantly increase the number of Design iterations. The results of this study suggest that with adequate advancement in each of these areas, FPGA Design Productivity can be increased by 25X over current practice.
Brent Nelson - One of the best experts on this subject based on the ideXlab platform.
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FPL - Increasing Design Productivity through Core Reuse, Meta-data Encapsulation, and Synthesis
2010 International Conference on Field Programmable Logic and Applications, 2010Co-Authors: Adam T. Arnesen, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, Kevin Ellsworth, Michael WirthlinAbstract:This paper presents a novel IP core reuse strategy which reduces Design time from days to hours for communication circuits such as digital radio receivers. This Design Productivity is obtained by leveraging a highly parameterized library of communication specific cores. These cores are described in IP-XACT XML with vendor extensions describing the timing behavior of their communication interfaces. A synthesis tool, called Ogre, was created that generates the communication interfaces between cores described in IP-XACT and synthesizes full Designs from structural synchronous dataflow specifications. Design Productivity improvements are demonstrated with several radio receiver Designs.
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Increasing Design Productivity through core reuse, meta-data encapsulation, and synthesis
Proceedings - 2010 International Conference on Field Programmable Logic and Applications FPL 2010, 2010Co-Authors: Adam Arnesen, Derrick Gibelyou, Travis Haroldsen, Jared Havican, Marc Padilla, Brent Nelson, Michael Rice, Kevin Ellsworth, Michael WirthlinAbstract:This paper presents a novel IP core reuse strategy which reduces Design time from days to hours for communication circuits such as digital radio receivers. This Design Productivity is obtained by leveraging a highly parameterized library of communication specific cores. These cores are described in IP-XACT XML with vendor extensions describing the timing behavior of their communication interfaces. A synthesis tool, called Ogre, was created that generates the communication interfaces between cores described in IP-XACT and synthesizes full Designs from structural synchronous dataflow specifications. Design Productivity improvements are demonstrated with several radio receiver Designs.
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ARC - FPGA Design Productivity a discussion of the state of the art and a research agenda
Lecture Notes in Computer Science, 2008Co-Authors: Brent NelsonAbstract:Summary form only given. As configurable computing matures there is continued interest in Design Productivity. While configurable computing machines (CCMs) are touted as re-usable, re-configurable platforms for accelerated computing, the Design processes and tools employed to map applications to such platforms may have more in common with hardware ASIC Design tools and processes than with conventional software development tools and processes. To address this there continues to be research in the community on higher-level languages, reusable core libraries, improved CAD tools, debug infrastructure, etc. but little focus on the big picture. That is, how do all these pieces fit together into a comprehensive approach for improving Design Productivity? Is a 10x increase in Design Productivity feasible in the next few years? How about 20x? What are the key research problems that must be solved? What are the most promising approaches to solving these problems? My talk will focus on these questions and will draw from the results of two events related to FPGA Design Productivity which were held recently. First, the day before FPT'2009, a workshop is being held at Taiwan National University to discuss these questions with all FPT attendees invited to participate. Details are found on the FPT conference website. Special guest speakers at the workshop will be asked to provide their viewpoints on FPGA Design Productivity and components of a research agenda to increase Productivity over the next 5-10 year horizon. Second, during the past year in the United States, two multi-university research teams have focused on developing and outlining a research agenda to address FPGA Design Productivity, culminating in a workshop held in Salt Lake City during June 2008. My talk will discuss the current challenges in FPGA Design Productivity and address a range of solutions, based in part on the results of the above two workshops as well as other efforts going on in the research community.
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Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows
2008Co-Authors: Michael Wirthlin, Brent Nelson, Brad Hutchings, Peter Athanas, Shawn A. BohnerAbstract:Abstract : Interest is growing in the use of FPGA devices for high-performance, efficient parallel computation. The large amount of programmable logic, internal routing, and memory can be used to perform a wide variety of high-performance computation more efficiently than traditional microprocessor-based computing architectures. The Productivity of FPGA Design, however, is very low. FPGA Design is very time consuming and requires low-level hardware Design skills. This study investigated this FPGA Design Productivity problem and identified potential solutions that will provide revolutionary improvements in Design Productivity. Three research areas that must be addressed to achieve such improvements are significant improvement in reuse of FPGA circuits, identification and deployment of higher level Design abstractions, and increasing the number of turns per day to significantly increase the number of Design iterations. The results of this study suggest that with adequate advancement in each of these areas, FPGA Design Productivity can be increased by 25X over current practice.
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FPGA Design Productivity a discussion of the state of the art and a research agenda
2008 International Conference on Field-Programmable Technology, 2008Co-Authors: Brent NelsonAbstract:Summary form only given. As configurable computing matures there is continued interest in Design Productivity. While configurable computing machines (CCMs) are touted as re-usable, re-configurable platforms for accelerated computing, the Design processes and tools employed to map applications to such platforms may have more in common with hardware ASIC Design tools and processes than with conventional software development tools and processes. To address this there continues to be research in the community on higher-level languages, reusable core libraries, improved CAD tools, debug infrastructure, etc. but little focus on the big picture. That is, how do all these pieces fit together into a comprehensive approach for improving Design Productivity? Is a 10x increase in Design Productivity feasible in the next few years? How about 20x? What are the key research problems that must be solved? What are the most promising approaches to solving these problems? My talk will focus on these questions and will draw from the results of two events related to FPGA Design Productivity which were held recently. First, the day before FPT'2009, a workshop is being held at Taiwan National University to discuss these questions with all FPT attendees invited to participate. Details are found on the FPT conference website. Special guest speakers at the workshop will be asked to provide their viewpoints on FPGA Design Productivity and components of a research agenda to increase Productivity over the next 5-10 year horizon. Second, during the past year in the United States, two multi-university research teams have focused on developing and outlining a research agenda to address FPGA Design Productivity, culminating in a workshop held in Salt Lake City during June 2008. My talk will discuss the current challenges in FPGA Design Productivity and address a range of solutions, based in part on the results of the above two workshops as well as other efforts going on in the research community.
Maxime Pelcat - One of the best experts on this subject based on the ideXlab platform.
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Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators
IEEE Embedded Systems Letters, 2019Co-Authors: Claudio Rubattu, Francesca Palumbo, Rubén Salvador, Jocelyn Sérot, Karol Desnos, Luigi Raffo, Maxime PelcatAbstract:Domain-specific acceleration is now a must for all the computing spectrum, going from high performance computing to embedded systems. Unfortunately, system specialization is by nature a nightmare from the Design Productivity perspective. Nevertheless, in contexts where kernels to be accelerated are intrinsically streaming oriented, the combination of dataflow (DF) models of computation with coarse-grained reconfiguration (CGR) architectures can be particularly handful. In this letter we introduce a novel methodology to assemble and characterize virtually reconfigurable accelerators based on DF and functional programming principles, capable of addressing Design Productivity issues for CGR accelerators. The main advantage of the proposed methodology is accurate IP-level latency predictability improving Design space exploration when compared with state-of-the-art high-level synthesis.
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Models, Methods and Tools for Bridging the Design Productivity Gap of Embedded Signal Processing Systems
2017Co-Authors: Maxime PelcatAbstract:The complexity of systems is currently growing faster than the Productivity of system Designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating Design costs. This Habilitation a Diriger des Recherches (HDR) report present models, methods and tool for improving the Design Productivity (DP) of embedded Digital Signal Processing systems and reducing this Design Productivity Gap. The notion of Design Productivity is commonly used without defining it. This report starts by precisely defining DP before presenting different methods to improve and evaluate it. In a first part, methods based on Models of Computation (MoCs) are explored. They constitute our past and present work on the subject. Dataflow MoCs are used to study application properties (liveness, schedulability, parallelism, etc.) at a high level of abstraction, often before implementation details are known. We have over the last seven years explored how dataflow MoCs can influence the performance and Design efforts of modern multicore Digital Signal Processing systems. In the second part of this report, the focus is shifted on the notion of Model of Architecture (MoA) we recently introduced. Parallel and heterogeneous platforms are becoming ever more complex. MoAs have the potential to counteract the DP reduction caused by this rising complexity and constitute the main subject I intend to continue studying in the next years. MoAs, and in general Model-Based Design, can have a great impact on future Design methods. Together with the concepts of Cyber-Physical Systems (CPS), Approximate Computing and Rapid Prototyping, they represent new opportunities for reducing the Design Productivity Gap of future DSP systems.
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Design Productivity of a high level synthesis compiler versus HDL
2016 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS), 2016Co-Authors: Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François BerryAbstract:The complexity of hardware systems is currently growing faster than the Productivity of system Designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating Design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description. The proposed Design Productivity metric evaluates the trade-off between Design efficiency and implementation quality. The method is generic enough to be used for comparing several HLS methods of different natures, opening opportunities for further progress in Design Productivity. To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed. Versions of the sub-pixel interpolation filter from the MPEG HEVC standard are implemented and a Design Productivity gain of 2.3× in average is measured for the CAPH HLS method. It results from an average gain in Design time of 4.4× and an average loss in quality of 1.9×.
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SAMOS - Design Productivity of a high level synthesis compiler versus HDL
2016 International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS), 2016Co-Authors: Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François BerryAbstract:The complexity of hardware systems is currently growing faster than the Productivity of system Designers and programmers. This phenomenon is called Design Productivity Gap and results in inflating Design costs. In this paper, the notion of Design Productivity is precisely defined, as well as a metric to assess the Design Productivity of a High-Level Synthesis (HLS) method versus a manual hardware description. The proposed Design Productivity metric evaluates the trade-off between Design efficiency and implementation quality. The method is generic enough to be used for comparing several HLS methods of different natures, opening opportunities for further progress in Design Productivity. To demonstrate the Design Productivity evaluation method, an HLS compiler based on the CAPH language is compared to manual VHDL writing. The causes that make VHDL lower level than CAPH are discussed. Versions of the sub-pixel interpolation filter from the MPEG HEVC standard are implemented and a Design Productivity gain of 2.3× in average is measured for the CAPH HLS method. It results from an average gain in Design time of 4.4× and an average loss in quality of 1.9x.
N. Tsubaki - One of the best experts on this subject based on the ideXlab platform.
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ASP-DAC - VCore-based platform for SoC Design
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003Co-Authors: Y. Onishi, M. Muraoka, M. Utsuki, N. TsubakiAbstract:The reuse-based Design paradigm is the key to improve the Design Productivity of SoCs (System on a Chip). However, SoC Designers have difficulty in using conventional IPs (Intellectual Property) because they don't have enough variability, it is difficult to customize them. In this paper, we propose the variability of VCores (Virtual Cores) and show VCores are superior to IPs for system-level Design property. Based on VCores, we have developed a VCore-based platform. We show the SoC Design Productivity will be improved by using VCores and the VCore-based platform.
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VCore-based platform for SoC Design
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference 2003., 2003Co-Authors: Y. Onishi, M. Muraoka, M. Utsuki, N. TsubakiAbstract:The reuse-based Design paradigm is the key to improve the Design Productivity of SoCs (system on a chip). However, SoC Designers have difficulty in using conventional IPs (intellectual property) because they do not have enough variability; it is difficult to customize them. In this paper, we propose the variability of VCores (virtual cores) and show VCores are superior to IPs for system-level Design properties. Based on VCores, we have developed a VCore-based platform. We show that SoC Design Productivity is improved by using VCores and the VCore-based platform.