The Experts below are selected from a list of 78264 Experts worldwide ranked by ideXlab platform

Markus Valtiner - One of the best experts on this subject based on the ideXlab platform.

  • adhesive barnacle peptides exhibit a steric driven Design Rule to enhance adhesion between asymmetric surfaces
    Colloids and Surfaces B: Biointerfaces, 2017
    Co-Authors: Sangeetha Raman, Lukas Malms, Thomas Utzig, Buddha Ratna Shrestha, Philipp Stock, Shankar Krishnan, Markus Valtiner
    Abstract:

    Barnacles exhibit superior underwater adhesion simply through sequencing of the 21 proteinogenic amino acids, without post processing or using special amino acids. Here, we measure and discuss the molecular interaction of two distinct and recurring short peptide sequences (Bp1 and Bp2) inspired from the surface binding 19kDa protein from the barnacle attachment interface. Using self-assembled monolayer (SAMs) of known physical and chemical properties on molecularly smooth gold substrates in 5mM NaCl at pH 7.3, (1) the adsorption mechanisms of the barnacle inspired peptides are explored using quartz crystal microbalance, and (2) adhesion mediating properties are measured using the surface force apparatus. The hydrophobic Bp1 peptide with a cysteine residue adsorbs irreversibly onto Au surfaces due to thiol bond formation, while on hydrophobic CH3 SAM surface, the interactions are hydrophobic in nature. Interestingly, Bp2 that contains both hydrophobic and protonated amine units exhibits asymmetric bridging with an exceptionally high adhesion energy up to 100mJ/m2 between mica and both gold and CH3 SAM. Surprisingly on hydrophilic surfaces such as COOH- or OH-SAMs both peptides fail to show any interactions, implying the necessity of surface charge to promote bridging. Our results provide insights into the molecular aspects of manipulating and utilizing barnacle-mediated peptides to promote or inhibit underwater adhesion.

Takumi Yamaguchi - One of the best experts on this subject based on the ideXlab platform.

  • a 2 0 spl mu m pixel pitch mos image sensor with 1 5 transistor pixel and an amorphous si color filter
    IEEE Transactions on Electron Devices, 2006
    Co-Authors: Masahiro Kasano, Mitsuyoshi Mori, Shigetaka Kasuga, Takahiko Murata, Y Inaba, Takumi Yamaguchi
    Abstract:

    In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m Design Rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine Design Rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.

  • a 2 0 spl mu m pixel pitch mos image sensor with an amorphous si film color filter
    International Solid-State Circuits Conference, 2005
    Co-Authors: Masahiro Kasano, Mitsuyoshi Mori, Shigetaka Kasuga, Takahiko Murata, Y Inaba, Takumi Yamaguchi
    Abstract:

    A CMOS image sensor with an amorphous Si film color filter is implemented on a standard Si process. The color filter thickness is less than 100 nm. The sensor achieves a 30% aperture ratio by a 1.5 transistor/pixel architecture and a 0.15 /spl mu/m Design Rule.

Masahiro Kasano - One of the best experts on this subject based on the ideXlab platform.

  • a 2 0 spl mu m pixel pitch mos image sensor with 1 5 transistor pixel and an amorphous si color filter
    IEEE Transactions on Electron Devices, 2006
    Co-Authors: Masahiro Kasano, Mitsuyoshi Mori, Shigetaka Kasuga, Takahiko Murata, Y Inaba, Takumi Yamaguchi
    Abstract:

    In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m Design Rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine Design Rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.

  • a 2 0 spl mu m pixel pitch mos image sensor with an amorphous si film color filter
    International Solid-State Circuits Conference, 2005
    Co-Authors: Masahiro Kasano, Mitsuyoshi Mori, Shigetaka Kasuga, Takahiko Murata, Y Inaba, Takumi Yamaguchi
    Abstract:

    A CMOS image sensor with an amorphous Si film color filter is implemented on a standard Si process. The color filter thickness is less than 100 nm. The sensor achieves a 30% aperture ratio by a 1.5 transistor/pixel architecture and a 0.15 /spl mu/m Design Rule.

T Kawaai - One of the best experts on this subject based on the ideXlab platform.

  • a 70 nm 16 gb 16 level cell nand flash memory
    IEEE Journal of Solid-state Circuits, 2008
    Co-Authors: Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, K Iwasa, Michio Nakagawa, Masaki Fujiu, T Shimizu, Mitsuaki Honma, S Hoshi, T Kawaai
    Abstract:

    A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm Design Rule has been developed . This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash, and quadruple bit density comparing to single-bit (SLC) NAND flash memory with the same Design Rule. New programming method suppresses the floating gate coupling effect and enabled the narrow distribution for 16LC. The cache-program function can be achievable without any additional latches. Optimization of programming sequence achieves 0.62 MB/s programming throughput. This 16-level NAND flash memory technology reduces the cost per bit and improves the memory density even more.

  • a 70nm 16gb 16 level cell nand flash memory
    Symposium on VLSI Circuits, 2007
    Co-Authors: Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, K Iwasa, Michio Nakagawa, Masaki Fujiu, T Shimizu, Mitsuaki Honma, S Hoshi, T Kawaai
    Abstract:

    A 16 Gb 16-level-cell (16LC) NAND flash memory using 70 nm Design Rule has been developed. This 16LC NAND flash memory can store 4 bits in a cell which enabled double bit density comparing to 4-level-cell (4LC) NAND flash with the same Design Rule. New programming method achieves 0.62 MB/s programming throughput.

Takahiko Murata - One of the best experts on this subject based on the ideXlab platform.

  • a 2 0 spl mu m pixel pitch mos image sensor with 1 5 transistor pixel and an amorphous si color filter
    IEEE Transactions on Electron Devices, 2006
    Co-Authors: Masahiro Kasano, Mitsuyoshi Mori, Shigetaka Kasuga, Takahiko Murata, Y Inaba, Takumi Yamaguchi
    Abstract:

    In this paper, an ultrafine pixel size (2.0/spl times/2.0 /spl mu/m/sup 2/) MOS image sensor with very high sensitivity is developed. The key technologies that realize the MOS image sensor are a newly developed pixel circuit configuration (1.5 transistor/pixel), a fine 0.15-/spl mu/m Design Rule, and an amorphous Si color filter (Si-CF). In the new pixel circuit configuration, a unit pixel consists of one photodiode, one transfer transistor, and an amplifier circuit with two transistors that are shared by four neighboring pixels. Thus, the unit pixel has only 1.5 transistors. The fine Design Rule of 0.15 /spl mu/m enables reduction of wiring area by 40%. As a result, a high aperture ratio of 30% is achieved. A newly developed Si-CF realizes the 1/10 thickness of that of the conventional organic-pigment CF, giving rise to high light-collection efficiency. With these three technologies combined, a high sensitivity of 3400 electrons/lx/spl middot/s is achieved even with a pixel size of 2.0/spl times/2.0 /spl mu/m/sup 2/.

  • a 2 0 spl mu m pixel pitch mos image sensor with an amorphous si film color filter
    International Solid-State Circuits Conference, 2005
    Co-Authors: Masahiro Kasano, Mitsuyoshi Mori, Shigetaka Kasuga, Takahiko Murata, Y Inaba, Takumi Yamaguchi
    Abstract:

    A CMOS image sensor with an amorphous Si film color filter is implemented on a standard Si process. The color filter thickness is less than 100 nm. The sensor achieves a 30% aperture ratio by a 1.5 transistor/pixel architecture and a 0.15 /spl mu/m Design Rule.