The Experts below are selected from a list of 249 Experts worldwide ranked by ideXlab platform

Mashroor Ahmad Khan - One of the best experts on this subject based on the ideXlab platform.

  • Analysis and Optimum Plan for 3-Step Step-Stress Accelerated Life Tests with Lomax Model Under Progressive Type-I Censoring
    Communications in Mathematics and Statistics, 2018
    Co-Authors: N. Chandra, Mashroor Ahmad Khan
    Abstract:

    In this paper, the optimum test plan and parameter estimation for 3-step step-Stress accelerated life tests in the presence of modified progressive Type-I censoring are discussed. It is assumed that the lifetime of test units follows a Lomax distribution with log of characteristic life being quadratic function of Stress level. The maximum likelihood and Bayesian method are used to obtain the point and interval estimators of the model parameters. The Bayes estimates are obtained using Markov chain Monte Carlo simulation based on Gibbs sampling. The optimum plan for 3-step step-Stress test under modified progressive Type-I censoring is developed which minimizes the asymptotic variance of the maximum likelihood estimators of log of scale parameter at Design Stress. Finally, the numerical study with sensitivity analysis is presented to illustrate the proposed study.

  • Optimum quadratic step-Stress accelerated life test plan for Weibull distribution under type-I censoring
    International Journal of System Assurance Engineering and Management, 2017
    Co-Authors: N. Chandra, Mashroor Ahmad Khan, G. Gopal
    Abstract:

    This paper presents the optimum Stress changing times for 3-step, step Stress accelerated life testing under the cumulative exposure model with type-I censoring. The lifetimes of test units are assumed to follow Weibull distribution. The scale parameter of the Weibull failure time at constant Stress level is assumed to be a log-quadratic function of the Stress level. We derive an optimum test plans to minimize the asymptotic variance of maximum likelihood estimator of given p th percentile of the distribution at a Design Stress. The optimum test plan based on simulated observations is illustrated through a numerical example. The maximum likelihood estimates and asymptotic interval estimates are obtained using R software.

Remus Teodorescu - One of the best experts on this subject based on the ideXlab platform.

  • temperature dependency analysis and correction methods of in situ power loss estimation for crystalline silicon modules undergoing potential induced degradation Stress testing
    Progress in Photovoltaics, 2015
    Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus Teodorescu
    Abstract:

    We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated Stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module Designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at Stress temperature and the degradation measured at 25 °C, dependent on module Design, Stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids Stress transients while ramping to and from the Stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on crystalline silicon photovoltaic modules show a mismatch between the power degradation measured at Stress temperature and the power degradation measured at 25 °C, which depends on module Design, Stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic module power at standard test conditions using superposition of the dark I-V curve measured at the elevated Stress temperature during potential-induced degradation testing, avoiding Stress transients while ramping to and from the Stress temperature

  • Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for crystalline silicon modules undergoing potential‐induced degradation Stress testing
    Progress in Photovoltaics: Research and Applications, 2015
    Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus Teodorescu
    Abstract:

    We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated Stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module Designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at Stress temperature and the degradation measured at 25 °C, dependent on module Design, Stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids Stress transients while ramping to and from the Stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on crystalline silicon photovoltaic modules show a mismatch between the power degradation measured at Stress temperature and the power degradation measured at 25 °C, which depends on module Design, Stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic module power at standard test conditions using superposition of the dark I-V curve measured at the elevated Stress temperature during potential-induced degradation testing, avoiding Stress transients while ramping to and from the Stress temperature

N. Chandra - One of the best experts on this subject based on the ideXlab platform.

  • Analysis and Optimum Plan for 3-Step Step-Stress Accelerated Life Tests with Lomax Model Under Progressive Type-I Censoring
    Communications in Mathematics and Statistics, 2018
    Co-Authors: N. Chandra, Mashroor Ahmad Khan
    Abstract:

    In this paper, the optimum test plan and parameter estimation for 3-step step-Stress accelerated life tests in the presence of modified progressive Type-I censoring are discussed. It is assumed that the lifetime of test units follows a Lomax distribution with log of characteristic life being quadratic function of Stress level. The maximum likelihood and Bayesian method are used to obtain the point and interval estimators of the model parameters. The Bayes estimates are obtained using Markov chain Monte Carlo simulation based on Gibbs sampling. The optimum plan for 3-step step-Stress test under modified progressive Type-I censoring is developed which minimizes the asymptotic variance of the maximum likelihood estimators of log of scale parameter at Design Stress. Finally, the numerical study with sensitivity analysis is presented to illustrate the proposed study.

  • Optimum quadratic step-Stress accelerated life test plan for Weibull distribution under type-I censoring
    International Journal of System Assurance Engineering and Management, 2017
    Co-Authors: N. Chandra, Mashroor Ahmad Khan, G. Gopal
    Abstract:

    This paper presents the optimum Stress changing times for 3-step, step Stress accelerated life testing under the cumulative exposure model with type-I censoring. The lifetimes of test units are assumed to follow Weibull distribution. The scale parameter of the Weibull failure time at constant Stress level is assumed to be a log-quadratic function of the Stress level. We derive an optimum test plans to minimize the asymptotic variance of maximum likelihood estimator of given p th percentile of the distribution at a Design Stress. The optimum test plan based on simulated observations is illustrated through a numerical example. The maximum likelihood estimates and asymptotic interval estimates are obtained using R software.

Corinne E Packard - One of the best experts on this subject based on the ideXlab platform.

  • temperature dependency analysis and correction methods of in situ power loss estimation for crystalline silicon modules undergoing potential induced degradation Stress testing
    Progress in Photovoltaics, 2015
    Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus Teodorescu
    Abstract:

    We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated Stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module Designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at Stress temperature and the degradation measured at 25 °C, dependent on module Design, Stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids Stress transients while ramping to and from the Stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on crystalline silicon photovoltaic modules show a mismatch between the power degradation measured at Stress temperature and the power degradation measured at 25 °C, which depends on module Design, Stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic module power at standard test conditions using superposition of the dark I-V curve measured at the elevated Stress temperature during potential-induced degradation testing, avoiding Stress transients while ramping to and from the Stress temperature

  • Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for crystalline silicon modules undergoing potential‐induced degradation Stress testing
    Progress in Photovoltaics: Research and Applications, 2015
    Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus Teodorescu
    Abstract:

    We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated Stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module Designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at Stress temperature and the degradation measured at 25 °C, dependent on module Design, Stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids Stress transients while ramping to and from the Stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on crystalline silicon photovoltaic modules show a mismatch between the power degradation measured at Stress temperature and the power degradation measured at 25 °C, which depends on module Design, Stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic module power at standard test conditions using superposition of the dark I-V curve measured at the elevated Stress temperature during potential-induced degradation testing, avoiding Stress transients while ramping to and from the Stress temperature

Sergiu Spataru - One of the best experts on this subject based on the ideXlab platform.

  • temperature dependency analysis and correction methods of in situ power loss estimation for crystalline silicon modules undergoing potential induced degradation Stress testing
    Progress in Photovoltaics, 2015
    Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus Teodorescu
    Abstract:

    We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated Stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module Designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at Stress temperature and the degradation measured at 25 °C, dependent on module Design, Stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids Stress transients while ramping to and from the Stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on crystalline silicon photovoltaic modules show a mismatch between the power degradation measured at Stress temperature and the power degradation measured at 25 °C, which depends on module Design, Stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic module power at standard test conditions using superposition of the dark I-V curve measured at the elevated Stress temperature during potential-induced degradation testing, avoiding Stress transients while ramping to and from the Stress temperature

  • Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for crystalline silicon modules undergoing potential‐induced degradation Stress testing
    Progress in Photovoltaics: Research and Applications, 2015
    Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus Teodorescu
    Abstract:

    We propose a method for in situ characterization of the photovoltaic module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated Stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several crystalline silicon module Designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the modules. The results using the superposition principle show a mismatch between the power degradation measured at Stress temperature and the degradation measured at 25 °C, dependent on module Design, Stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids Stress transients while ramping to and from the Stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on crystalline silicon photovoltaic modules show a mismatch between the power degradation measured at Stress temperature and the power degradation measured at 25 °C, which depends on module Design, Stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic module power at standard test conditions using superposition of the dark I-V curve measured at the elevated Stress temperature during potential-induced degradation testing, avoiding Stress transients while ramping to and from the Stress temperature