The Experts below are selected from a list of 261 Experts worldwide ranked by ideXlab platform

Albert Wang - One of the best experts on this subject based on the ideXlab platform.

  • Full-chip ESD protection Design Verification method for HV ICs with multiple power domains
    2017 12th IEEE Conference on Industrial Electronics and Applications (ICIEA), 2017
    Co-Authors: Feilong Zhang, Fei Lu, Chenkun Wang, Qi Chen, Cheng Li, Albert Wang
    Abstract:

    This paper reports a new full-chip circuit level electrostatic discharge (ESD) protection circuit Design Verification technique for mixed-signal high-voltage (HV) high-power power management ICs (PMIC) featuring multiple power domains. This method, validated in a 28nm CMOS and 30V BCD process, can be used for Design Verification of PMIC system-on-a-chip (SoC) ICs for many applications, such as power electronics ICs for smart grids and power management ICs for smartphones.

  • Function-based ESD protection circuit Design Verification for BGA pad-ring array
    2015 IEEE 11th International Conference on ASIC (ASICON), 2015
    Co-Authors: Li Wang, Fei Lu, Albert Wang, Zongyu Dong, Xin Wang, Chen Zhang, Bin Zhao, He Tang
    Abstract:

    This paper reports a new function-based on-chip electrostatic discharge (ESD) protection circuit Design Verification technique for integrated circuits (ICs) using ball grid ball (BGA) pad-ring array. The ESD protection Design Verification method is enabled by ESD simulation including ESD behavior modeling and BGS pad-ring metal routing evaluation through ESD extraction using the ESDExtractor CAD tool for whole-chip pad-ring array. Full function-based ESD protection Design simulation and Verification is applied to a visible light communication (VLC) transceiver IC using large BGA pad-ring array, which was implemented in a commercial 180nm BCD technology.

  • whole chip esd protection Design Verification by cad
    2009 31st EOS ESD Symposium, 2009
    Co-Authors: Xin Wang, Albert Wang, Bin Zhao, He Tang, Qiang Fang, Hui Zhao, Rouying Zhan, Chai Ean Gill, Yumei Zhou, Gary Zhang
    Abstract:

    CAD is essential to simulation, Design and synthesis of on-chip ESD protection circuitry to ensure Design prediction and Verification at whole-chip level. This paper reviews a new function-based ESD CAD platform and Design methodology, including arbitrary ESD protection device extraction algorithm, smart parametric ESD checking mechanism, smart ESD zapping simulation flow and new CAD tools enabling whole-chip ESD protection Design Verification. Practical Design examples are presented.

Fei Lu - One of the best experts on this subject based on the ideXlab platform.

  • Full-chip ESD protection Design Verification method for HV ICs with multiple power domains
    2017 12th IEEE Conference on Industrial Electronics and Applications (ICIEA), 2017
    Co-Authors: Feilong Zhang, Fei Lu, Chenkun Wang, Qi Chen, Cheng Li, Albert Wang
    Abstract:

    This paper reports a new full-chip circuit level electrostatic discharge (ESD) protection circuit Design Verification technique for mixed-signal high-voltage (HV) high-power power management ICs (PMIC) featuring multiple power domains. This method, validated in a 28nm CMOS and 30V BCD process, can be used for Design Verification of PMIC system-on-a-chip (SoC) ICs for many applications, such as power electronics ICs for smart grids and power management ICs for smartphones.

  • Function-based ESD protection circuit Design Verification for BGA pad-ring array
    2015 IEEE 11th International Conference on ASIC (ASICON), 2015
    Co-Authors: Li Wang, Fei Lu, Albert Wang, Zongyu Dong, Xin Wang, Chen Zhang, Bin Zhao, He Tang
    Abstract:

    This paper reports a new function-based on-chip electrostatic discharge (ESD) protection circuit Design Verification technique for integrated circuits (ICs) using ball grid ball (BGA) pad-ring array. The ESD protection Design Verification method is enabled by ESD simulation including ESD behavior modeling and BGS pad-ring metal routing evaluation through ESD extraction using the ESDExtractor CAD tool for whole-chip pad-ring array. Full function-based ESD protection Design simulation and Verification is applied to a visible light communication (VLC) transceiver IC using large BGA pad-ring array, which was implemented in a commercial 180nm BCD technology.

Feilong Zhang - One of the best experts on this subject based on the ideXlab platform.

  • Full-chip ESD protection Design Verification method for HV ICs with multiple power domains
    2017 12th IEEE Conference on Industrial Electronics and Applications (ICIEA), 2017
    Co-Authors: Feilong Zhang, Fei Lu, Chenkun Wang, Qi Chen, Cheng Li, Albert Wang
    Abstract:

    This paper reports a new full-chip circuit level electrostatic discharge (ESD) protection circuit Design Verification technique for mixed-signal high-voltage (HV) high-power power management ICs (PMIC) featuring multiple power domains. This method, validated in a 28nm CMOS and 30V BCD process, can be used for Design Verification of PMIC system-on-a-chip (SoC) ICs for many applications, such as power electronics ICs for smart grids and power management ICs for smartphones.

J. Park - One of the best experts on this subject based on the ideXlab platform.

  • ICCD - An efficient symbolic Design Verification system
    Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93, 1993
    Co-Authors: J. Park, M.r. Mercer
    Abstract:

    Verifying the correctness of logic Design has been an important problem for a long time. But there have been no efficient Design Verification tools for very large circuits. We present an efficient symbolic Design Verification method for very large circuits which exploits the properties of OPDDs (ordered partial decision diagrams). By symbolically extracting and simulating test patterns with OPDDs our Design Verification system provides time and space advantages over existing methods. >

  • An efficient symbolic Design Verification system
    Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93, 1993
    Co-Authors: J. Park
    Abstract:

    Verifying the correctness of logic Design has been an important problem for a long time. But there have been no efficient Design Verification tools for very large circuits. We present an efficient symbolic Design Verification method for very large circuits which exploits the properties of OPDDs (ordered partial decision diagrams). By symbolically extracting and simulating test patterns with OPDDs our Design Verification system provides time and space advantages over existing methods.

Cheng Li - One of the best experts on this subject based on the ideXlab platform.

  • Full-chip ESD protection Design Verification method for HV ICs with multiple power domains
    2017 12th IEEE Conference on Industrial Electronics and Applications (ICIEA), 2017
    Co-Authors: Feilong Zhang, Fei Lu, Chenkun Wang, Qi Chen, Cheng Li, Albert Wang
    Abstract:

    This paper reports a new full-chip circuit level electrostatic discharge (ESD) protection circuit Design Verification technique for mixed-signal high-voltage (HV) high-power power management ICs (PMIC) featuring multiple power domains. This method, validated in a 28nm CMOS and 30V BCD process, can be used for Design Verification of PMIC system-on-a-chip (SoC) ICs for many applications, such as power electronics ICs for smart grids and power management ICs for smartphones.