The Experts below are selected from a list of 306 Experts worldwide ranked by ideXlab platform

Khalil Najafi - One of the best experts on this subject based on the ideXlab platform.

  • A detailed study of yield and reliability for vacuum packages fabricated in a Wafer-level Au-Si eutectic bonding process
    TRANSDUCERS 2009 - 2009 International Solid-State Sensors Actuators and Microsystems Conference, 2009
    Co-Authors: Jay Mitchell, Khalil Najafi
    Abstract:

    An Au-Si eutectic Wafer-level bonding process was developed for low-temperature vacuum packaging of MEMS Devices. Using Au-Si eutectic bonding, Devices were encapsulated by bonding a silicon cap Wafer to a Device Wafer. Micromachined Pirani vacuum sensors were encapsulated in order to characterize the packaged pressures. These packages had cavity dimensions of 2.3×2.3 mm with a depth of 90 µm. Yields of 84.6% and 94.1% were achieved in packages with bond ring widths of 100 and 150 µm. With the use of getters and a pre-bond outgassing step, pressures from ≪3.7 to 23.3 mTorr were achieved. Furthermore, pressures were shown to remain stable to within ±2.5 mTorr for over 4 years of testing.

  • Reliability and characterization of micro-packages in a Wafer level Au-Si eutectic vacuum bonding process
    Advances in Electronic Packaging Parts A B and C, 2005
    Co-Authors: Jay Mitchell, G.r. Lahiji, Khalil Najafi
    Abstract:

    A Au-Si eutectic vacuum packaging process was evaluated using high sensitivity poly-Si Pirani vacuum sensors. Encapsulation of Devices was achieved by bonding a silicon cap Wafer to a Device Wafer using a Au-Si eutectic solder at above 390°C in a vacuum bonder. The Au-Si eutectic solder encircled the Devices, providing an airtight seal. The Pirani gauges were encapsulated and tested over a period of several months in order to determine base pressures and leak/outgassing rates of the micro-cavities. Packaged Devices without getters showed initial pressures from 2 to 12 Torr with initial leak/outgassing rates of −0.073 to 80 Torr/year. Using getters, pressures as low as 5 mTorr have been achieved with leak/outgassing rates of

  • Transfer of metal MEMS packages using a Wafer-level solder transfer technique
    IEEE Transactions on Advanced Packaging, 2005
    Co-Authors: W.c. Welch, Junseok Chae, Khalil Najafi
    Abstract:

    This paper presents a modular, low profile, Wafer-level encapsulation technology for microelectromechanical systems (MEMS) packaging. Electroplated caps are formed on top of a solder transfer layer previously deposited on a carrier Wafer, then simultaneously transferred and bonded to a Device Wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the carrier Wafer and TLP bonding of the cap to the Device Wafer during bonding. The bond and transfer cycle has a maximum temperature of 300/spl deg/C and lasts about 2.5 h. This approach has been demonstrated with nickel (Ni) caps as thin as 5 microns, with thicker caps certainly possible, ranging in size from 200 /spl mu/m to 1 mm. They were transferred with a lead-tin (Pb-Sn) solder layer and bonded with nickel-tin (Ni-Sn) TLP bonding with greater than 99% transfer yield across the Wafer.

  • Wafer Bonding Technology FOR VACUUM PACKAGING USING GOLD
    2004
    Co-Authors: Yuhai Mei, Roientan Lahiji, Khalil Najafi
    Abstract:

    In this paper successful silicon Wafer bonding technology using gold-silicon eutectic is reported. The Wafers, Device Wafer and cap Wafer are bonded in vacuum. Device Wafer is terminated on the surface with a bond layer that can be single crystal silicon, a layer of polysilicon, gold or any other suitable metal, dielectric or semiconductor layer, and the cap Wafer contains an electroplated gold bond ring. Bonding has been carried out in a standard Wafer bonder by performing a pre-bake at 300°C and then pressing the Wafers together by 1Mpa and subsequent bonding at a temperature of about 400°C for 30 minutes. Bonding yield of more than 95% is achieved on 4" silicon Wafers with excellent reproducibility. Excellent coverage of soft eutectic bonding over non-planar surfaces has been investigated using 1.2mm-thick insulated feedthroughs of polysilicon, which shows a good flow of eutectic material over the feedthroughs. Thin film polysilicon diaphragm (~2.5mm-thick) and micro-Pirani gauge have been used to monitor and measure the low-pressure inside the packaged vacuum cavity. It is more than one year that we are monitoring the pressure by the amount of buckling in the diaphragm, and so far no pressure drop is observed. Direct pressure measurement is also underway by the vacuum packaged floating Pirani gauges fabricated inside the Device Wafer. It also has been shown that polysilicon is a better source material in gold- silicon eutectic formation as it bonds at relatively lower temperature than single crystal silicon.

  • Transfer of metal MEMS packages using a Wafer-level solder sacrificial layer
    18th IEEE International Conference on Micro Electro Mechanical Systems 2005. MEMS 2005., 1
    Co-Authors: W.c. Welch, Khalil Najafi
    Abstract:

    This paper presents a modular, low profile, Wafer-level encapsulation technology for 0-level MEMS packaging. Electroplated caps are formed on a carrier Wafer then simultaneously transferred and bonded to a Device Wafer by a novel solder transfer method and transient liquid phase (TLP) bonding technology. The solder transfer method is enabled by the dewetting of the solder transfer layer from the carrier Wafer, and TLP bonding of the cap to the Device Wafer during bonding. The nickel-tin TLP bond and transfer cycle has a maximum temperature of 300 /spl deg/C and lasts about 2.5 hours. This approach has been demonstrated with nickel caps 5 microns thick, ranging in size from 200 /spl mu/m 1 mm. They were transferred with a lead-tin transfer solder layer and bonded with nickel-tin TLP bonding with greater than 99% transfer yield across the Wafer.

F. Fournel - One of the best experts on this subject based on the ideXlab platform.

  • Development and adhesion characterization of a silicon Wafer for temporary bonding
    International Journal of Adhesion and Adhesives, 2018
    Co-Authors: P. Montmeat, T. Enot, G. Enyedi, M. Pellat, J. Thooris, F. Fournel
    Abstract:

    The development of a silicon temporary carrier for thin Wafer handling for 3D applications was investigated. Process selection and optimization ended up with a silicon carrier entirely covered with an antistick layer based on a fluorinated polymer. The carrier preparation was quite easy because only one coating was used and no sticking edge zone was needed onto the carrier. The fluorinated coating led to a very hydrophobic behavior. When bonded with a thermoplastic glue, it also exhibited very antiadhesive properties because the adherence was as low as 0.4 J/m(2) and lower than the adherence of a stack without any antiadhesive layer (above 4 J/m(2)). The carrier was nevertheless suitable for different back side processes in 300 mm grinding, chemical cleaning, chemical mechanical polishing and silicon oxide deposition. Compared with a commercial carrier, it exhibited the same level of performance for the integration. The proposed carrier was compatible with a mechanical debonding of a thinned bonded structure with a silicon Device Wafer of 80 pm. The carrier recycling was possible without any new preparation.

  • Temporary polymer bonding for the manufacturing of thin Wafers: An innovative low temperature process
    Materials Science in Semiconductor Processing, 1
    Co-Authors: P. Montmeat, T. Enot, L. Bally, J. Dechamp, F. Fournel
    Abstract:

    Abstract The study deals with the handling of thin Wafers in 3D integration. It concerns the fabrication of 300 mm Wafers in industrial tools. Usually, the manufacturing is based on a temporary bonding process performed at 200 °C using a thermoplastic adhesive. In that condition bonding, thinning and dismounting are satisfactory. Moreover, the adhesive flattening during bonding results in an excellent thickness uniformity of the bonded pairs, with a small total thickness variation (TTV) value suitable for 3D integration. If the temperature is 150 °C or lower, the adhesive thickness uniformity is not acceptable anymore. An innovative temporary bonding process at low temperature has thus been developed. It consists in a carrier fabrication with highly uniform adhesive thickness. The standard coated adhesive is flattened with a first reversible temporary bonding at 210 °C. After a first dismounting, this carrier is then bonded to the target Device Wafer with a low bonding temperature, from 110 °C to 150 °C. Due to the pre-flattening, 80 μm thick silicon films with an excellent TTV value can thus be obtained even with a low bonding temperature required by the Device Wafer. Moreover, after the Device Wafer thinning, the final dismounting can be performed without any antisticking layer.

Yuelin Wang - One of the best experts on this subject based on the ideXlab platform.

  • Wafer level vacuum packaged resonator with in-situ Au-Al eutectic Re-Distribution layer
    SENSORS 2012 IEEE, 2012
    Co-Authors: Guoqiang Wu, Dehui Xu, Errong Jing, Bin Xiong, Yuelin Wang
    Abstract:

    In this paper, a Wafer level vacuum packaged resonator with in-situ Au-Al eutectic Re-Distribution layer is demonstrated. A cap Wafer with silicon bumps and electrical feedthroughs is bonded together with a MEMS resonator Wafer using Wafer level glass frit bonding technology. The silicon bumps provide close contact for the aluminum layer on the cap Wafer and the gold layer on the Device Wafer, on which a gold-aluminum (Au-Al) eutectic is formed. The in-situ Au-Al eutectic layer achieve electrical interconnections between the cap Wafer and the Device Wafer, which realizes the redistribution of the electrical feedthroughs of the MEMS resonator on the cap Wafer. The formation mechanism of the Au-Al eutectic is illustrated. The Au-Al eutectic is observed through the FD3/SEM and IR images and is analyzed using EDX. The measured dynamic performance of the packaged MEMS resonator is presented in this paper. Experimental results show that the Wafer-level vacuum packaged MEMS resonator results in over 100× higher quality factor (Q) than the resonator vibrating in atmosphere pressure. The experimental results indicate that vacuum about 3 mbar can be sealed in this approach.

  • Redistribution of Electrical Interconnections for Three-Dimensional Wafer-Level Packaging With Silicon Bumps
    IEEE Electron Device Letters, 2012
    Co-Authors: Guoqiang Wu, Dehui Xu, Bin Xiong, Yuelin Wang
    Abstract:

    In this letter, an approach to the redistribution of electrical interconnections is investigated for potential application in 3-D Wafer-level packaging. A cap Wafer with silicon bumps and electrical feedthroughs is bonded together with a Device Wafer using Wafer-level glass-frit bonding technology. During the bonding process, the mechanical bond is performed by glass-frit bonding to form hermetic packaging. Simultaneously, the silicon bumps provide close contact for the electrical feedthroughs on the cap Wafer and the metal pads on the Device Wafer, on which a gold-aluminum eutectic is formed to achieve electrical interconnections between the cap Wafer and the Device Wafer. Moreover, the silicon bumps provide a way to control well the height of the bonding materials. This process not only realizes a Wafer-level hermetic sealing but also achieves the redistribution of electrical interconnections. Application of this approach for a high performance MEMS resonator is demonstrated, which illustrates the feasibility of this process.

M. Bartek - One of the best experts on this subject based on the ideXlab platform.

  • RF–MEMS Wafer-level packaging using through-Wafer interconnect
    Sensors and Actuators A: Physical, 2008
    Co-Authors: J. Tian, S. Sosin, Jacopo Iannacci, R. Gaddi, M. Bartek
    Abstract:

    Abstract In this paper, development of a Wafer-level packaging (WLP) process suitable for RF–MEMS applications is presented. The packaging concept is based on a high-resistivity silicon capping substrate that is Wafer-level bonded to an RF–MEMS Device Wafer providing MEMS Device protection and vertical electrical signal interconnect. The capping substrate contains Cu-plated through-Wafer electrical vias and optional through-substrate cavities allowing for hybrid integration. The RF–MEMS Device Wafer and the capping substrate are bonded using either solder reflow or an electrically conductive adhesive. After solder bump formation and singulation, this packaging solution results in surface-mount technology compatible components. Moreover, the presented WLP solution allows hybrid integration of additional IC dies that are flip-chip bonded within the capping substrate cavities.

P. Montmeat - One of the best experts on this subject based on the ideXlab platform.

  • Development and adhesion characterization of a silicon Wafer for temporary bonding
    International Journal of Adhesion and Adhesives, 2018
    Co-Authors: P. Montmeat, T. Enot, G. Enyedi, M. Pellat, J. Thooris, F. Fournel
    Abstract:

    The development of a silicon temporary carrier for thin Wafer handling for 3D applications was investigated. Process selection and optimization ended up with a silicon carrier entirely covered with an antistick layer based on a fluorinated polymer. The carrier preparation was quite easy because only one coating was used and no sticking edge zone was needed onto the carrier. The fluorinated coating led to a very hydrophobic behavior. When bonded with a thermoplastic glue, it also exhibited very antiadhesive properties because the adherence was as low as 0.4 J/m(2) and lower than the adherence of a stack without any antiadhesive layer (above 4 J/m(2)). The carrier was nevertheless suitable for different back side processes in 300 mm grinding, chemical cleaning, chemical mechanical polishing and silicon oxide deposition. Compared with a commercial carrier, it exhibited the same level of performance for the integration. The proposed carrier was compatible with a mechanical debonding of a thinned bonded structure with a silicon Device Wafer of 80 pm. The carrier recycling was possible without any new preparation.

  • Temporary polymer bonding for the manufacturing of thin Wafers: An innovative low temperature process
    Materials Science in Semiconductor Processing, 1
    Co-Authors: P. Montmeat, T. Enot, L. Bally, J. Dechamp, F. Fournel
    Abstract:

    Abstract The study deals with the handling of thin Wafers in 3D integration. It concerns the fabrication of 300 mm Wafers in industrial tools. Usually, the manufacturing is based on a temporary bonding process performed at 200 °C using a thermoplastic adhesive. In that condition bonding, thinning and dismounting are satisfactory. Moreover, the adhesive flattening during bonding results in an excellent thickness uniformity of the bonded pairs, with a small total thickness variation (TTV) value suitable for 3D integration. If the temperature is 150 °C or lower, the adhesive thickness uniformity is not acceptable anymore. An innovative temporary bonding process at low temperature has thus been developed. It consists in a carrier fabrication with highly uniform adhesive thickness. The standard coated adhesive is flattened with a first reversible temporary bonding at 210 °C. After a first dismounting, this carrier is then bonded to the target Device Wafer with a low bonding temperature, from 110 °C to 150 °C. Due to the pre-flattening, 80 μm thick silicon films with an excellent TTV value can thus be obtained even with a low bonding temperature required by the Device Wafer. Moreover, after the Device Wafer thinning, the final dismounting can be performed without any antisticking layer.