The Experts below are selected from a list of 6945 Experts worldwide ranked by ideXlab platform

Dejan Markovic - One of the best experts on this subject based on the ideXlab platform.

  • A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
    IEEE Journal of Solid-State Circuits, 2012
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm2 in 65-nm CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for -5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22× reduction in power per sensing bandwidth compared with prior work.

  • A 7.4mW 200MS/s wideband spectrum sensing Digital Baseband processor for cognitive radios
    2011
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing with channel-specific threshold and sensing time is integrated in 1.64mm2 in 65nm CMOS. The processor achieves detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for −5dB SNR within a 50ms sensing time. The chip dissipates 7.4mW for a 200MHz sensing bandwidth. A 22x reduction in power per sensing bandwidth is achieved compared to prior work.

  • a 7 4mw 200ms s wideband spectrum sensing Digital Baseband processor for cognitive radios
    Symposium on VLSI Circuits, 2011
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing with channel-specific threshold and sensing time is integrated in 1.64mm2 in 65nm CMOS. The processor achieves detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for −5dB SNR within a 50ms sensing time. The chip dissipates 7.4mW for a 200MHz sensing bandwidth. A 22x reduction in power per sensing bandwidth is achieved compared to prior work.

Chia-hsiang Yang - One of the best experts on this subject based on the ideXlab platform.

  • A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
    IEEE Journal of Solid-State Circuits, 2012
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm2 in 65-nm CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for -5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22× reduction in power per sensing bandwidth compared with prior work.

  • A 7.4mW 200MS/s wideband spectrum sensing Digital Baseband processor for cognitive radios
    2011
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing with channel-specific threshold and sensing time is integrated in 1.64mm2 in 65nm CMOS. The processor achieves detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for −5dB SNR within a 50ms sensing time. The chip dissipates 7.4mW for a 200MHz sensing bandwidth. A 22x reduction in power per sensing bandwidth is achieved compared to prior work.

  • a 7 4mw 200ms s wideband spectrum sensing Digital Baseband processor for cognitive radios
    Symposium on VLSI Circuits, 2011
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing with channel-specific threshold and sensing time is integrated in 1.64mm2 in 65nm CMOS. The processor achieves detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for −5dB SNR within a 50ms sensing time. The chip dissipates 7.4mW for a 200MHz sensing bandwidth. A 22x reduction in power per sensing bandwidth is achieved compared to prior work.

Danijela Cabric - One of the best experts on this subject based on the ideXlab platform.

  • A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
    IEEE Journal of Solid-State Circuits, 2012
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing processor with 200-kHz resolution over 200-MHz bandwidth is integrated in 1.64 mm2 in 65-nm CMOS. The processor uses adaptive channel-specific threshold and sensing time to achieve detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for -5-dB SNR and adjacent-band interferers of 30-dB INR within a 50-ms sensing time. The chip power and area are minimized by jointly considering algorithm, architecture, and circuit parameters. The chip dissipates 7.4 mW for a 200-MHz sensing bandwidth, which is a 22× reduction in power per sensing bandwidth compared with prior work.

  • A 7.4mW 200MS/s wideband spectrum sensing Digital Baseband processor for cognitive radios
    2011
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing with channel-specific threshold and sensing time is integrated in 1.64mm2 in 65nm CMOS. The processor achieves detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for −5dB SNR within a 50ms sensing time. The chip dissipates 7.4mW for a 200MHz sensing bandwidth. A 22x reduction in power per sensing bandwidth is achieved compared to prior work.

  • a 7 4mw 200ms s wideband spectrum sensing Digital Baseband processor for cognitive radios
    Symposium on VLSI Circuits, 2011
    Co-Authors: Chia-hsiang Yang, Danijela Cabric, Dejan Markovic
    Abstract:

    A Digital Baseband cognitive radio spectrum sensing with channel-specific threshold and sensing time is integrated in 1.64mm2 in 65nm CMOS. The processor achieves detection probability ≥ 0.9 and false-alarm probability ≤ 0.1 for −5dB SNR within a 50ms sensing time. The chip dissipates 7.4mW for a 200MHz sensing bandwidth. A 22x reduction in power per sensing bandwidth is achieved compared to prior work.

Xin'an Wang - One of the best experts on this subject based on the ideXlab platform.

  • Design and implementation of a HBC Digital Baseband system for two-hop extension star network
    2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2016
    Co-Authors: Hao Chen, Bo Wang, Zhongmin Lin, Ying Zhang, Xin'an Wang
    Abstract:

    In Human Body Communication (HBC) system, low power is still one of the most important research issues for monitoring nodes supplied by battery. Utilizing two-hop extension star network topology is an efficient measure to reduce the average transmission power consumption and improve the stability. This paper proposes a Digital Baseband system for low duty cycle and low load network. When the nodes are far apart from hub relatively, the system can change the working mode to selecting relay mode automatically according to the network environment. The whole Baseband system is verified on FPGA prototype platform with 2Mb/s data rate for ECG(electrocardiogram) monitoring. Under SMIC 0.13um CMOS process, the area and power are 133370 um2 and 1.619mW for node Digital Baseband, and 79246 um2 and 0.674mW for hub Digital Baseband.

  • Design and realization of UHF RFID reader Digital Baseband
    2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
    Co-Authors: Zhaoyang Guo, Xin'an Wang, Shanshan Yong, Zhang Fangni, Zheng Zheng
    Abstract:

    This paper presents an ASIC design and implementation of Digital Baseband system for UHF RFID reader supporting the ISO18000-6C protocol. The Digital Baseband consists of five parts: Digital Baseband receiver, Digital Baseband transmitter, controller, CRC (Cyclic Redundancy Check) and serial interface modules. We present a new more secure and effective encode algorithm, TPP (Truncated Pulse Position encoding), which develops from PIE (Pulse Interval Encoding). In addition, we improve the signal adjuster of the Digital Baseband receiver and transmitter for decoding and encoding more exactly. Under 0.18µm CMOS process, the area of reader Digital Baseband is 3032802µm2 and the power is 105.215mw.

  • Design of a Novel Digital Baseband for UHF RFID Tag
    Applied Mechanics and Materials, 2014
    Co-Authors: Xin'an Wang
    Abstract:

    This paper presents a novel low-power Digital Baseband for UHF RFID tag. The design is complied with a modified ISO 18000-6C protocol. In order to reduce the peak power, module-reuse and other advanced low power techniques are applied. And a novel Baseband architecture is discussed, which fulfills the protocol functions and reduces power consumption. The whole tag chip, including Digital Baseband, RF/analog frontend and memory, has been taped out using TSMC 0.18um CMOS process. The chip area is 89234 um2 excluding test pads. Its power consumption is 11.63uw under 1.1v power supply.

  • An intelligent and reusable verification platform based on UVM for RFID Digital Baseband
    2014 IEEE International Conference on Electron Devices and Solid-State Circuits, 2014
    Co-Authors: Chang Liu, Zheng Xie, Qingqing Liu, Xin'an Wang
    Abstract:

    The verification kit for RFID system based on hardware is difficult for engineers to debug. Therefore, in this paper an intelligent verification environment for RFID using UVM is built to improve efficiency. Firstly, a design of RFID Digital Baseband is introduced. Then an intelligent structure based on UVM and comprised of four test modes is presented. With the aspect-oriented and transaction level modeling, a reusable verification with high efficiency has been achieved.

  • Design and Automatic System Verification of Digital Baseband for UHF RFID Tag
    International Journal of Electronics and Electrical Engineering, 2013
    Co-Authors: Zheng Xie, Xin'an Wang, Ying Cao
    Abstract:

    This paper presents the design and automatic system verification of Digital Baseband for Ultra High Frequency (UHF) radio frequency identification (RFID) tag, which is complied with a modified ISO 18000-6C protocol. Module-reuse approach and low power techniques are applied in the Digital Baseband to reduce the power consumption. And a novel verification strategy is discussed, which decreases the verification cycle greatly via function test mode and coverage test mode, and generates testcases automatically by using coverage-driven random-based approach. The strategy has many merits, such as a hierarchical architecture for reuse, inspecting low power design though assertion, locating bugs accurately, and linking C++ via direct programming interface (DPI). The tag chip is designed in a 0.18um CMOS process with a size of 89234 um. Simulation results verify the efficiency of the proposed methods. 

J. Fridman - One of the best experts on this subject based on the ideXlab platform.

  • ICASSP (5) - Cached memory performance characterization of a wireless Digital Baseband processor
    2004 IEEE International Conference on Acoustics Speech and Signal Processing, 1
    Co-Authors: S. Kannaw, M. Allen, J. Fridman
    Abstract:

    We present performance analysis results of the MSP500 Digital Baseband (DBB) platform, a system developed at Analog Devices Inc., targeted at cellular handsets supporting the GSM, GPRS, and EDGE communication standards. We focus on a particular member of the MSP500 family, the AD6532 device, which integrates a Blackfin/spl reg/ core, and examine the execution time performance of a number of wireless physical layer software components from the perspective of an instruction- and data-cached memory hierarchy. The Blackfin is a 16-bit fixed-point core that combines some of the best features of DSPs and micro-controllers, and has support for a cached memory system.