The Experts below are selected from a list of 53745 Experts worldwide ranked by ideXlab platform
Bruce D Smith - One of the best experts on this subject based on the ideXlab platform.
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how good are standard debt contracts stochastic versus nonstochastic monitoring in a costly state Verification Environment
Social Science Research Network, 1998Co-Authors: John H Boyd, Bruce D SmithAbstract:We investigate ex ante efficient contracts in an Environment in which implementation is costless. In this Environment, standard debt contracts will typically not be optimal. Optimal contracts may involve defaults, even in states in which the borrower is fully able to repay. We then examine the welfare costs of arbitrarily restricting the set of feasible contracts to standard debt contracts. When model parameters are calibrated to realistic values, the welfare loss from exogenously imposing this restriction is extremely small. Thus, if implementation costs are actually nontrivial (as seem likely), standard debt contracts will be (very close to) optimal.
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how good are standard debt contracts stochastic versus nonstochastic monitoring in a costly state Verification Environment
The Journal of Business, 1994Co-Authors: John H Boyd, Bruce D SmithAbstract:The authors investigate ex ante efficient contracts in an Environment in which implementation is costless. In this Environment, standard debt contracts will typically not be optimal. Optimal contracts may involve defaults even in states in which the borrower is fully able to repay. The authors then examine the welfare costs of arbitrarily restricting the set of feasible contracts to standard debt contracts. When model parameters are calibrated to realistic values, the welfare loss from exogenously imposing this restriction is extremely small. Thus, if implementation costs are actually nontrivial (as seems likely), standard debt contracts will be (very close to) optimal. Copyright 1994 by University of Chicago Press.
John H Boyd - One of the best experts on this subject based on the ideXlab platform.
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how good are standard debt contracts stochastic versus nonstochastic monitoring in a costly state Verification Environment
Social Science Research Network, 1998Co-Authors: John H Boyd, Bruce D SmithAbstract:We investigate ex ante efficient contracts in an Environment in which implementation is costless. In this Environment, standard debt contracts will typically not be optimal. Optimal contracts may involve defaults, even in states in which the borrower is fully able to repay. We then examine the welfare costs of arbitrarily restricting the set of feasible contracts to standard debt contracts. When model parameters are calibrated to realistic values, the welfare loss from exogenously imposing this restriction is extremely small. Thus, if implementation costs are actually nontrivial (as seem likely), standard debt contracts will be (very close to) optimal.
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how good are standard debt contracts stochastic versus nonstochastic monitoring in a costly state Verification Environment
The Journal of Business, 1994Co-Authors: John H Boyd, Bruce D SmithAbstract:The authors investigate ex ante efficient contracts in an Environment in which implementation is costless. In this Environment, standard debt contracts will typically not be optimal. Optimal contracts may involve defaults even in states in which the borrower is fully able to repay. The authors then examine the welfare costs of arbitrarily restricting the set of feasible contracts to standard debt contracts. When model parameters are calibrated to realistic values, the welfare loss from exogenously imposing this restriction is extremely small. Thus, if implementation costs are actually nontrivial (as seems likely), standard debt contracts will be (very close to) optimal. Copyright 1994 by University of Chicago Press.
Gila Kamhi - One of the best experts on this subject based on the ideXlab platform.
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efficient debugging in a formal Verification Environment
International Journal on Software Tools for Technology Transfer, 2003Co-Authors: Fady Copty, Amitai Irron, Osnat Weissberg, Nathan P Kropp, Gila KamhiAbstract:In this paper, we emphasize the importance of efficient debugging in formal Verification and present capabilities that we have developed in order to aid debugging in Intel's Formal Verification Environment. We have given the name Counter-Example Wizard to the bundle of capabilities that we have developed to address the needs of the Verification engineer in the context of counter-example diagnosis and rectification. The novel features of the Counter-Example Wizard are the multivalue counter-example annotation, constraint-based debugging, and multiple counter-example generation mechanisms. Our experience with the Verification of real-life Intel designs shows that these capabilities complement one another and can help the Verification engineer diagnose and fix a reported failure. We use real-life Verification cases to illustrate how our system solution can significantly reduce the time spent in the loop of model checking, specification, and design modification.
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multiple counterexample guided iterative abstraction refinement an industrial evaluation
Tools and Algorithms for Construction and Analysis of Systems, 2003Co-Authors: Marcelo Glusman, Gila Kamhi, Sela Madorhaim, Ranan Fraer, Moshe Y VardiAbstract:In this paper, we describe a completely automated framework for iterative abstraction refinement that is fully integrated into a formal-Verification Environment. This Environment consists of three basic software tools: Forecast, a BDD-based model checker, Thunder, a SAT-based bounded model checker, and MCE, a technology for multiple-counterexample analysis. In our framework, the initial abstraction is chosen relative to the property under Verification. The abstraction is model checked by Forecast; in case of failure, a counter example is returned. Our framework includes an abstract counterexample analyzer module that applies techniques for bounded model checking to check whether the abstract counter example holds in the concrete model. If it does, it is extended to a concrete counter example. This important capability is provided as a separate tool that also addresses one of the major problems of Verification by manual abstraction. If the counter example is spurious, we use a novel refinement heuristic based on MCE to guide the refinement. After the part of the abstract model to be refined is chosen, our refinement algorithm computes a new abstraction that includes as much logic as possible without adding too many new variables, therefore striking a balance between refining the abstraction and keeping its size manageable. We demonstrate the effectiveness of our framework on challenging Intel designs that were not amenable to BDD-based model-checking approaches.
Abhishek Jain - One of the best experts on this subject based on the ideXlab platform.
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unified and modular modeling and functional Verification framework of real time image signal processors
Vlsi Design, 2016Co-Authors: Abhishek Jain, Richa GuptaAbstract:In VLSI industry, image signal processing algorithms are developed and evaluated using software models before implementation of RTL and firmware. After the finalization of the algorithm, software models are used as a golden reference model for the image signal processor (ISP) RTL and firmware development. In this paper, we are describing the unified and modular modeling framework of image signal processing algorithms used for different applications such as ISP algorithms development, reference for hardware (HW) implementation, reference for firmware (FW) implementation, and bit-true certification. The universal Verification methodology- (UVM-) based functional Verification framework of image signal processors using software reference models is described. Further, IP-XACT based tools for automatic generation of functional Verification Environment files and model map files are described. The proposed framework is developed both with host interface and with core using virtual register interface (VRI) approach. This modeling and functional Verification framework is used in real-time image signal processing applications including cellphone, smart cameras, and image compression. The main motivation behind this work is to propose the best efficient, reusable, and automated framework for modeling and Verification of image signal processor (ISP) designs. The proposed framework shows better results and significant improvement is observed in product Verification time, Verification cost, and quality of the designs.
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early development of uvm based Verification Environment of image signal processing designs using tlm reference model of rtl
International Journal of Advanced Computer Science and Applications, 2014Co-Authors: Abhishek Jain, Hima Gupta, Sandeep Jana, Krishna KumarAbstract:With semiconductor industry trend of “smaller the better”, from an idea to a final product, more innovation on product portfolio and yet remaining competitive and profitable are few criteria which are culminating into pressure and need for more and more innovation for CAD flow, process management and project execution cycle. Project schedules are very tight and to achieve first silicon success is key for projects. This necessitates quicker Verification with better coverage matrix. Quicker Verification requires early development of the Verification Environment with wider test vectors without waiting for RTL to be available. In this paper, we are presenting a novel approach of early development of reusable multi-language Verification flow, by addressing four major activities of Verification – 1. Early creation of Executable Specification 2. Early creation of Verification Environment 3. Early development of test vectors and 4. Better and increased Re-use of blocks Although this paper focuses on early development of UVM based Verification Environment of Image Signal Processing designs using TLM Reference Model of RTL, same concept can be extended for non-image signal processing designs.
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Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
arXiv: Other Computer Science, 2013Co-Authors: Abhishek Jain, Giuseppe Bonanno, Hima Gupta, Ajay GoyalAbstract:In this paper,we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient Verification of Image Signal Processing IP's/SoC's. With the tight schedules on all projects it is important to have a strong Verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and Verification of corner cases through pseudo random test scenarios is required. Also, standardization of Verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level Verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools. The main aim of development of this Generic and automatic Verification Environment is to develop an efficient and unified Verification Environment (at IP/Subsystem/SoC Level) which reuses the already developed Verification components and also sequences written at IP/Subsystem level can be reused at SoC Level both with Host BFM and actual Core using Incisive Software Extension (ISX) and Virtual Register Interface (VRI)/Verification Abstraction Layer (VAL) approaches. IP-XACT based tools are used for automatically configuring the Environment for various imaging IPs/SoCs.
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Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
International Journal of VLSI Design & Communication Systems, 2012Co-Authors: Abhishek Jain, Giuseppe Bonanno, Hima Gupta, Ajay GoyalAbstract:In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient Verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong Verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and Verification of corner cases through pseudo random test scenarios is required. Also, standardization of Verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level Verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools. The main aim of development of this Generic and automatic Verification Environment is to develop an efficient and unified Verification Environment (at IP/Subsystem/SoC Level) which reuses the already developed Verification components and also sequences written at IP/Subsystem level can be reused at SoC Level both with Host BFM and actual Core using Incisive Software Extension (ISX) and Virtual Register Interface (VRI)/Verification Abstraction Layer (VAL) approaches. IP-XACT based tools are used for automatically configuring the Environment for various imaging IPs/SoCs. Although this paper focus on Generic System Verilog Universal Verification Methodology based reusable Verification Environment built for imaging IPs/SoCs. Same concept can be extended for non imaging IPs/SoCs.
Ajay Goyal - One of the best experts on this subject based on the ideXlab platform.
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Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
arXiv: Other Computer Science, 2013Co-Authors: Abhishek Jain, Giuseppe Bonanno, Hima Gupta, Ajay GoyalAbstract:In this paper,we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient Verification of Image Signal Processing IP's/SoC's. With the tight schedules on all projects it is important to have a strong Verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and Verification of corner cases through pseudo random test scenarios is required. Also, standardization of Verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level Verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools. The main aim of development of this Generic and automatic Verification Environment is to develop an efficient and unified Verification Environment (at IP/Subsystem/SoC Level) which reuses the already developed Verification components and also sequences written at IP/Subsystem level can be reused at SoC Level both with Host BFM and actual Core using Incisive Software Extension (ISX) and Virtual Register Interface (VRI)/Verification Abstraction Layer (VAL) approaches. IP-XACT based tools are used for automatically configuring the Environment for various imaging IPs/SoCs.
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Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for Efficient Verification of Image Signal Processing IPs/SoCs
International Journal of VLSI Design & Communication Systems, 2012Co-Authors: Abhishek Jain, Giuseppe Bonanno, Hima Gupta, Ajay GoyalAbstract:In this paper, we present Generic System Verilog Universal Verification Methodology based Reusable Verification Environment for efficient Verification of Image Signal Processing IP’s/SoC’s. With the tight schedules on all projects it is important to have a strong Verification methodology which contributes to First Silicon Success. Deploy methodologies which enforce full functional coverage and Verification of corner cases through pseudo random test scenarios is required. Also, standardization of Verification flow is needed. Previously, inside imaging group of ST, Specman (e)/Verilog based Verification Environment for IP/Subsystem level Verification and C/C++/Verilog based Directed Verification Environment for SoC Level Verification was used for Functional Verification. Different Verification Environments were used at IP level and SoC level. Different Verification/Validation Methodologies were used for SoC Verification across multiple sites. Verification teams were also looking for the ways how to catch bugs early in the design cycle? Thus, Generic System Verilog Universal Verification Methodology (UVM) based Reusable Verification Environment is required to avoid the problem of having so many methodologies and provides a standard unified solution which compiles on all tools. The main aim of development of this Generic and automatic Verification Environment is to develop an efficient and unified Verification Environment (at IP/Subsystem/SoC Level) which reuses the already developed Verification components and also sequences written at IP/Subsystem level can be reused at SoC Level both with Host BFM and actual Core using Incisive Software Extension (ISX) and Virtual Register Interface (VRI)/Verification Abstraction Layer (VAL) approaches. IP-XACT based tools are used for automatically configuring the Environment for various imaging IPs/SoCs. Although this paper focus on Generic System Verilog Universal Verification Methodology based reusable Verification Environment built for imaging IPs/SoCs. Same concept can be extended for non imaging IPs/SoCs.
