The Experts below are selected from a list of 3288 Experts worldwide ranked by ideXlab platform
T Nakagawa - One of the best experts on this subject based on the ideXlab platform.
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low power Video encoder decoder chip set for Digital vcrs
International Solid-State Circuits Conference, 1996Co-Authors: K Hasegawa, K Ohara, T Kamada, Y Nagaoka, Katsuhisa Yano, E Yamauchi, Takao Kashiro, T NakagawaAbstract:This paper describes the realization of a Video encoder/decoder chip set for the consumer use Digital Video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 Digital Component Video signal into the standard-definition Digital VCR (DV) format or decode the DV format signal into a Component Video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-/spl mu/m 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-/spl mu/m CMOS technology, contains about 500 k transistors on 71 mm/sup 2/ and 79 mm/sup 2/ die, respectively.
K Hasegawa - One of the best experts on this subject based on the ideXlab platform.
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low power Video encoder decoder chip set for Digital vcrs
International Solid-State Circuits Conference, 1996Co-Authors: K Hasegawa, K Ohara, T Kamada, Y Nagaoka, Katsuhisa Yano, E Yamauchi, Takao Kashiro, T NakagawaAbstract:This paper describes the realization of a Video encoder/decoder chip set for the consumer use Digital Video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 Digital Component Video signal into the standard-definition Digital VCR (DV) format or decode the DV format signal into a Component Video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-/spl mu/m 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-/spl mu/m CMOS technology, contains about 500 k transistors on 71 mm/sup 2/ and 79 mm/sup 2/ die, respectively.
K Ohara - One of the best experts on this subject based on the ideXlab platform.
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low power Video encoder decoder chip set for Digital vcrs
International Solid-State Circuits Conference, 1996Co-Authors: K Hasegawa, K Ohara, T Kamada, Y Nagaoka, Katsuhisa Yano, E Yamauchi, Takao Kashiro, T NakagawaAbstract:This paper describes the realization of a Video encoder/decoder chip set for the consumer use Digital Video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 Digital Component Video signal into the standard-definition Digital VCR (DV) format or decode the DV format signal into a Component Video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-/spl mu/m 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-/spl mu/m CMOS technology, contains about 500 k transistors on 71 mm/sup 2/ and 79 mm/sup 2/ die, respectively.
T Kamada - One of the best experts on this subject based on the ideXlab platform.
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low power Video encoder decoder chip set for Digital vcrs
International Solid-State Circuits Conference, 1996Co-Authors: K Hasegawa, K Ohara, T Kamada, Y Nagaoka, Katsuhisa Yano, E Yamauchi, Takao Kashiro, T NakagawaAbstract:This paper describes the realization of a Video encoder/decoder chip set for the consumer use Digital Video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 Digital Component Video signal into the standard-definition Digital VCR (DV) format or decode the DV format signal into a Component Video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-/spl mu/m 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-/spl mu/m CMOS technology, contains about 500 k transistors on 71 mm/sup 2/ and 79 mm/sup 2/ die, respectively.
Y Nagaoka - One of the best experts on this subject based on the ideXlab platform.
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low power Video encoder decoder chip set for Digital vcrs
International Solid-State Circuits Conference, 1996Co-Authors: K Hasegawa, K Ohara, T Kamada, Y Nagaoka, Katsuhisa Yano, E Yamauchi, Takao Kashiro, T NakagawaAbstract:This paper describes the realization of a Video encoder/decoder chip set for the consumer use Digital Video cassette recorder (VCR). The two chips with a 5 Mb external DRAM either encode the CCIR601 Digital Component Video signal into the standard-definition Digital VCR (DV) format or decode the DV format signal into a Component Video signal. The compression rate of the intraframe compression is about 1/6. The total power dissipation of the two LSI's is 142 mW at 2 V internal supply voltage, which is more than one order of magnitude smaller than the recently reported MPIEG2 (MP@ML) encoder systems. Low power was achieved primarily due to the compression scheme which is optimized for large-scale integration (LSI) implementation. The 0.5-/spl mu/m 2-V CMOS standard cell library was also effective in reducing the power consumption. Each chip, fabricated in two-layer metal 0.5-/spl mu/m CMOS technology, contains about 500 k transistors on 71 mm/sup 2/ and 79 mm/sup 2/ die, respectively.