The Experts below are selected from a list of 1356 Experts worldwide ranked by ideXlab platform

Hoi-jun Yoo - One of the best experts on this subject based on the ideXlab platform.

  • Bio-Medical CMOS ICs - Digital Hearing Aid and Cochlear Implant
    Bio-Medical CMOS ICs, 2010
    Co-Authors: Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    Approximately 70 million individuals worldwide suffer from Hearing loss, which makes it the most common sensory disorder in the world [1–3]. There are estimated 28 million individuals with Hearing loss in the United States. Hearing loss affects 17 in 1,000 children under the age of 18, with the incidence increasing with age. Approximately 314 in 1,000 people over the age of 65 have Hearing loss, and 40–50% of people 75 and older have Hearing loss.

  • Autonomous gain verification algorithm for a dual mode Digital Hearing Aid chip
    Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Inte, 2008
    Co-Authors: Sunyoung Kim, Long Yan, Minsu Kim, Joonsung Bae, Hoi-jun Yoo
    Abstract:

    A dual mode Digital Hearing Aid chip with real-time autonomous gain verifications algorithm is proposed and implemented. Four proposed gain models due to the different internal sound paths are analyzed to verify its usefulness. By adopting this algorithm, a real-ear Aided gain and a real-ear occluded gain which considers internal vent effect and leakage path effect are compared with conventional models. To evaluate this algorithm the implemented chip adopts two different modes; a Hearing Aid mode and a gain verification mode for a Hearing Aid operation and internal gain verification, respectively. The minimum and maximum convergence time of the presented algorithm covers 0.05 s at a 1 kHz input signal and 1.6 s at a 7.5 kHz input signal, respectively. The implemented chip dissipates less than 130 μW at a supply voltage of 0.9 V and occupies a 5.4 mm2 core are at a 0.18 μm CMOS technology.

  • a 0 9 v 96 mu w fully operational Digital Hearing Aid chip
    IEEE Journal of Solid-state Circuits, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A 0.9 V 96 muW fully operational low-power Digital Hearing Aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the Hearing Aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a Digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 muVrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mm in a 0.18 mum standard CMOS process.

  • a fully integrated Digital Hearing Aid chip with human factors considerations
    International Solid-State Circuits Conference, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A Digital Hearing-Aid chip integrates a pre-fitting verification algorithm to obtain gain fitting in two steps: coarse and fine. The internal ear canal modeling filter circuit enables the coarse fitting based on the shape of the external ear. Fine fitting verification is performed with external inputs. The 3.74mm2 chip draws less than 120muA from a single 0.9V supply in a 0.18mum CMOS technology.

  • a low power Digital signal processor with adaptive band activation for Digital Hearing Aid chip
    International Symposium on Circuits and Systems, 2007
    Co-Authors: Seung Jin Lee, Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    A low power Digital signal processor (DSP) for a Digital Hearing Aid chip is presented. The DSP integrates three programmable Digital finite impulse response (FIR) filters. Each FIR filter can have one pass-frequency out of seven preset frequencies so that only three FIR filters can have the same flexibility as seven filters. Additionally, a silence mode is defined in which only one filter is activated. A Digital voice activity detection circuit is implemented for this purpose. The DSP is implemented as part of a fully integrated Digital Hearing Aid chip. It uses a 0.18 mum CMOS process and occupies an area of 0.5 mm2. Power consumption is 25 muW in normal operating mode and 9 muW in silence mode at 0.9-V supply.

Seong-jun Song - One of the best experts on this subject based on the ideXlab platform.

  • A Fully Integrated Digital Hearing Aid Chip With Human Factors Considerations
    IEEE Journal of Solid-State Circuits, 2008
    Co-Authors: Seong-jun Song
    Abstract:

    A low-power Digital Hearing Aid chip with consideration of the human external ear characteristics according to the each individual user is proposed and implemented. It adopts the pre fitting verification algorithm (PREVA) to obtain the fast and accurate gain fitting and verification in two steps, coarse and fine gain fittings. The ear canal modeling filter circuit (EMC) which models the human external ear into the distributed LC filter enables the coarse gain fitting based on the shape of the external ear of the patient. The fine fitting verification is performed by the external inputs from the Hearing loss test results. To reduce the power consumption of the human factored Hearing Aid chip design, the multi-threshold preamplifier, the adaptive fitting Digital signal processor (DSP) with the filter reuse technique and the gated successive approximation ADC are designed and embedded to the Digital Hearing Aid chip. The dynamic range of the multi-threshold preamplifier exists from 0.45 V to 0.8 V and dissipates 32 muW from a single 0.9 V supply. The fabricated Digital Hearing Aid chip achieves the peak SNR of 81 dB in the overall system with 4.2 muV of input-referred noise voltage. The fabricated chip occupies the core area of 3.12times1.20 mm2 in a 0.18 mum standard CMOS technology and consumes only 107 muW from a single 0.9 V supply.

  • a 0 9 v 96 mu w fully operational Digital Hearing Aid chip
    IEEE Journal of Solid-state Circuits, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A 0.9 V 96 muW fully operational low-power Digital Hearing Aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the Hearing Aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a Digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 muVrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mm in a 0.18 mum standard CMOS process.

  • a fully integrated Digital Hearing Aid chip with human factors considerations
    International Solid-State Circuits Conference, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A Digital Hearing-Aid chip integrates a pre-fitting verification algorithm to obtain gain fitting in two steps: coarse and fine. The internal ear canal modeling filter circuit enables the coarse fitting based on the shape of the external ear. Fine fitting verification is performed with external inputs. The 3.74mm2 chip draws less than 120muA from a single 0.9V supply in a 0.18mum CMOS technology.

  • The Reference Ear Modeling Method for Internally Feedback Controlled Digital Hearing Aid Chip
    2007 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2007
    Co-Authors: Seong-jun Song
    Abstract:

    A reference ear modeling method for the real-time feedback controlled Digital Hearing Aid chip is proposed and implemented. In order to reduce the modeling complexity and enhance the programmability, new ear modeling method using the acoustic filter theory is adopted to the Digital Hearing Aid. To achieve the fully internal gain fitting and verification system, the responses from the damaged ear and the reference ear model are compared and the new gain parameters are processed for the multi-channel DSP. The Digital Hearing Aid chip with reference ear model is fabricated in 0.18 mum CMOS technology, has a core area of 3.1 mm times 1.2 mm and dissipates less than 120 muA.

  • The reference ear modeling method for internally feedback controlled Digital Hearing Aid chip.
    Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Inte, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A reference ear modeling method for the real-time feedback controlled Digital Hearing Aid chip is proposed and implemented. In order to reduce the modeling complexity and enhance the programmability, new ear modeling method using the acoustic filter theory is adopted to the Digital Hearing Aid. To achieve the fully internal gain fitting and verification system, the responses from the damaged ear and the reference ear model are compared and the new gain parameters are processed for the multi-channel DSP. The Digital Hearing Aid chip with reference ear model is fabricated in 0.18 microm CMOS technology, has a core area of 3.1 mm x 1.2 mm and dissipates less than 120 muA.

Sunyoung Kim - One of the best experts on this subject based on the ideXlab platform.

  • Bio-Medical CMOS ICs - Digital Hearing Aid and Cochlear Implant
    Bio-Medical CMOS ICs, 2010
    Co-Authors: Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    Approximately 70 million individuals worldwide suffer from Hearing loss, which makes it the most common sensory disorder in the world [1–3]. There are estimated 28 million individuals with Hearing loss in the United States. Hearing loss affects 17 in 1,000 children under the age of 18, with the incidence increasing with age. Approximately 314 in 1,000 people over the age of 65 have Hearing loss, and 40–50% of people 75 and older have Hearing loss.

  • Autonomous gain verification algorithm for a dual mode Digital Hearing Aid chip
    Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Inte, 2008
    Co-Authors: Sunyoung Kim, Long Yan, Minsu Kim, Joonsung Bae, Hoi-jun Yoo
    Abstract:

    A dual mode Digital Hearing Aid chip with real-time autonomous gain verifications algorithm is proposed and implemented. Four proposed gain models due to the different internal sound paths are analyzed to verify its usefulness. By adopting this algorithm, a real-ear Aided gain and a real-ear occluded gain which considers internal vent effect and leakage path effect are compared with conventional models. To evaluate this algorithm the implemented chip adopts two different modes; a Hearing Aid mode and a gain verification mode for a Hearing Aid operation and internal gain verification, respectively. The minimum and maximum convergence time of the presented algorithm covers 0.05 s at a 1 kHz input signal and 1.6 s at a 7.5 kHz input signal, respectively. The implemented chip dissipates less than 130 μW at a supply voltage of 0.9 V and occupies a 5.4 mm2 core are at a 0.18 μm CMOS technology.

  • a 0 9 v 96 mu w fully operational Digital Hearing Aid chip
    IEEE Journal of Solid-state Circuits, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A 0.9 V 96 muW fully operational low-power Digital Hearing Aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the Hearing Aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a Digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 muVrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mm in a 0.18 mum standard CMOS process.

  • a fully integrated Digital Hearing Aid chip with human factors considerations
    International Solid-State Circuits Conference, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A Digital Hearing-Aid chip integrates a pre-fitting verification algorithm to obtain gain fitting in two steps: coarse and fine. The internal ear canal modeling filter circuit enables the coarse fitting based on the shape of the external ear. Fine fitting verification is performed with external inputs. The 3.74mm2 chip draws less than 120muA from a single 0.9V supply in a 0.18mum CMOS technology.

  • a low power Digital signal processor with adaptive band activation for Digital Hearing Aid chip
    International Symposium on Circuits and Systems, 2007
    Co-Authors: Seung Jin Lee, Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    A low power Digital signal processor (DSP) for a Digital Hearing Aid chip is presented. The DSP integrates three programmable Digital finite impulse response (FIR) filters. Each FIR filter can have one pass-frequency out of seven preset frequencies so that only three FIR filters can have the same flexibility as seven filters. Additionally, a silence mode is defined in which only one filter is activated. A Digital voice activity detection circuit is implemented for this purpose. The DSP is implemented as part of a fully integrated Digital Hearing Aid chip. It uses a 0.18 mum CMOS process and occupies an area of 0.5 mm2. Power consumption is 25 muW in normal operating mode and 9 muW in silence mode at 0.9-V supply.

Namjun Cho - One of the best experts on this subject based on the ideXlab platform.

  • a 0 9 v 96 mu w fully operational Digital Hearing Aid chip
    IEEE Journal of Solid-state Circuits, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A 0.9 V 96 muW fully operational low-power Digital Hearing Aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the Hearing Aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a Digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 muVrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mm in a 0.18 mum standard CMOS process.

  • a fully integrated Digital Hearing Aid chip with human factors considerations
    International Solid-State Circuits Conference, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A Digital Hearing-Aid chip integrates a pre-fitting verification algorithm to obtain gain fitting in two steps: coarse and fine. The internal ear canal modeling filter circuit enables the coarse fitting based on the shape of the external ear. Fine fitting verification is performed with external inputs. The 3.74mm2 chip draws less than 120muA from a single 0.9V supply in a 0.18mum CMOS technology.

  • The reference ear modeling method for internally feedback controlled Digital Hearing Aid chip.
    Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Inte, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A reference ear modeling method for the real-time feedback controlled Digital Hearing Aid chip is proposed and implemented. In order to reduce the modeling complexity and enhance the programmability, new ear modeling method using the acoustic filter theory is adopted to the Digital Hearing Aid. To achieve the fully internal gain fitting and verification system, the responses from the damaged ear and the reference ear model are compared and the new gain parameters are processed for the multi-channel DSP. The Digital Hearing Aid chip with reference ear model is fabricated in 0.18 microm CMOS technology, has a core area of 3.1 mm x 1.2 mm and dissipates less than 120 muA.

  • ISSCC - A Fully Integrated Digital Hearing-Aid Chip with Human-Factors Considerations
    2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A Digital Hearing-Aid chip integrates a pre-fitting verification algorithm to obtain gain fitting in two steps: coarse and fine. The internal ear canal modeling filter circuit enables the coarse fitting based on the shape of the external ear. Fine fitting verification is performed with external inputs. The 3.74mm2 chip draws less than 120muA from a single 0.9V supply in a 0.18mum CMOS technology.

  • Dual Threshold Preamplifier and Multi-Channel DSP for Human Factored Digital Hearing Aid Chip
    2007 IEEE Symposium on VLSI Circuits, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    The low-power, high-programmability Digital Hearing Aid chip with consideration of human factors is implemented. To achieve the human factored design with low-power consumption, the dual threshold preamplifier and the multi-channel Digital signal processor (DSP) are designed. The dynamic range of the dual threshold preamplifier exists from 0.45-V to 0.8-V and dissipates 32-muW from a single 0.9-V supply. The core area of the preamplifier and the DSP are 0.057-mm2 and 0.5-mm2 respectively in a 0.18-mum CMOS technology.

Seung Jin Lee - One of the best experts on this subject based on the ideXlab platform.

  • a fully integrated Digital Hearing Aid chip with human factors considerations
    International Solid-State Circuits Conference, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A Digital Hearing-Aid chip integrates a pre-fitting verification algorithm to obtain gain fitting in two steps: coarse and fine. The internal ear canal modeling filter circuit enables the coarse fitting based on the shape of the external ear. Fine fitting verification is performed with external inputs. The 3.74mm2 chip draws less than 120muA from a single 0.9V supply in a 0.18mum CMOS technology.

  • a low power Digital signal processor with adaptive band activation for Digital Hearing Aid chip
    International Symposium on Circuits and Systems, 2007
    Co-Authors: Seung Jin Lee, Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    A low power Digital signal processor (DSP) for a Digital Hearing Aid chip is presented. The DSP integrates three programmable Digital finite impulse response (FIR) filters. Each FIR filter can have one pass-frequency out of seven preset frequencies so that only three FIR filters can have the same flexibility as seven filters. Additionally, a silence mode is defined in which only one filter is activated. A Digital voice activity detection circuit is implemented for this purpose. The DSP is implemented as part of a fully integrated Digital Hearing Aid chip. It uses a 0.18 mum CMOS process and occupies an area of 0.5 mm2. Power consumption is 25 muW in normal operating mode and 9 muW in silence mode at 0.9-V supply.

  • The reference ear modeling method for internally feedback controlled Digital Hearing Aid chip.
    Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and Biology Society. Annual Inte, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A reference ear modeling method for the real-time feedback controlled Digital Hearing Aid chip is proposed and implemented. In order to reduce the modeling complexity and enhance the programmability, new ear modeling method using the acoustic filter theory is adopted to the Digital Hearing Aid. To achieve the fully internal gain fitting and verification system, the responses from the damaged ear and the reference ear model are compared and the new gain parameters are processed for the multi-channel DSP. The Digital Hearing Aid chip with reference ear model is fabricated in 0.18 microm CMOS technology, has a core area of 3.1 mm x 1.2 mm and dissipates less than 120 muA.

  • ISCAS - A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid Chip
    2007 IEEE International Symposium on Circuits and Systems, 2007
    Co-Authors: Seung Jin Lee, Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    A low power Digital signal processor (DSP) for a Digital Hearing Aid chip is presented. The DSP integrates three programmable Digital finite impulse response (FIR) filters. Each FIR filter can have one pass-frequency out of seven preset frequencies so that only three FIR filters can have the same flexibility as seven filters. Additionally, a silence mode is defined in which only one filter is activated. A Digital voice activity detection circuit is implemented for this purpose. The DSP is implemented as part of a fully integrated Digital Hearing Aid chip. It uses a 0.18 mum CMOS process and occupies an area of 0.5 mm2. Power consumption is 25 muW in normal operating mode and 9 muW in silence mode at 0.9-V supply.

  • ISSCC - A Fully Integrated Digital Hearing-Aid Chip with Human-Factors Considerations
    2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007
    Co-Authors: Sunyoung Kim, Seong-jun Song, Seung Jin Lee, Namjun Cho, Hoi-jun Yoo
    Abstract:

    A Digital Hearing-Aid chip integrates a pre-fitting verification algorithm to obtain gain fitting in two steps: coarse and fine. The internal ear canal modeling filter circuit enables the coarse fitting based on the shape of the external ear. Fine fitting verification is performed with external inputs. The 3.74mm2 chip draws less than 120muA from a single 0.9V supply in a 0.18mum CMOS technology.