The Experts below are selected from a list of 279 Experts worldwide ranked by ideXlab platform

Lajos Gazsi - One of the best experts on this subject based on the ideXlab platform.

  • ICASSP - Adder-based digital signal processor architecture for 80 NS cycle time
    ICASSP '84. IEEE International Conference on Acoustics Speech and Signal Processing, 1
    Co-Authors: Alois Dipl.-ing. Rainer, W. Ulbrich, Lajos Gazsi
    Abstract:

    Architecture and performance tests of a digital signal processor with the following specific features are presented: Short cycle time of 80 ns, shift & add 2's complement arithmetic with saturation and sign-magnitude truncation operations, distributed memories with sophisticated address arithmetics, three stage pipelining, 16 bit instruction format, 20 bit internal data wordlength. In addition to standard problems sophisticated signal processing algorithms (wave digital filtering, Bergland's real-valued FFT, etc.) can powerfully be exploited. Furthermore, this concept is well-suited for implementing multiprocessor configurations.

Hoi-jun Yoo - One of the best experts on this subject based on the ideXlab platform.

  • a low power digital signal processor with adaptive band activation for digital hearing aid chip
    International Symposium on Circuits and Systems, 2007
    Co-Authors: Seung Jin Lee, Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    A low power digital signal processor (DSP) for a digital hearing aid chip is presented. The DSP integrates three programmable digital finite impulse response (FIR) filters. Each FIR filter can have one pass-frequency out of seven preset frequencies so that only three FIR filters can have the same flexibility as seven filters. Additionally, a silence mode is defined in which only one filter is activated. A digital voice activity detection circuit is implemented for this purpose. The DSP is implemented as part of a fully integrated digital hearing aid chip. It uses a 0.18 mum CMOS process and occupies an area of 0.5 mm2. Power consumption is 25 muW in normal operating mode and 9 muW in silence mode at 0.9-V supply.

  • ISCAS - A Low Power digital signal processor with Adaptive Band Activation for digital Hearing Aid Chip
    2007 IEEE International Symposium on Circuits and Systems, 2007
    Co-Authors: Seung Jin Lee, Sunyoung Kim, Hoi-jun Yoo
    Abstract:

    A low power digital signal processor (DSP) for a digital hearing aid chip is presented. The DSP integrates three programmable digital finite impulse response (FIR) filters. Each FIR filter can have one pass-frequency out of seven preset frequencies so that only three FIR filters can have the same flexibility as seven filters. Additionally, a silence mode is defined in which only one filter is activated. A digital voice activity detection circuit is implemented for this purpose. The DSP is implemented as part of a fully integrated digital hearing aid chip. It uses a 0.18 mum CMOS process and occupies an area of 0.5 mm2. Power consumption is 25 muW in normal operating mode and 9 muW in silence mode at 0.9-V supply.

  • ISCAS - A 10-/spl mu/W digital signal processor with adaptive-SNR monitoring for a sub-1V digital hearing aid
    2006 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: Jung-hee Yoo, Seong-jun Song, Sunyoung Kim, Namjun Cho, Hoi-jun Yoo
    Abstract:

    An ultra low-power digital signal processor (DSP) is proposed for the digital hearing aid. The DSP has a SNR monitor to vary its internal clock frequency in accordance with the input signal level. digital filters use hardwired barrel shifters in place of multipliers, and a parameter ROM provides filter parameters. The clock generator consumes only 1 /spl mu/W at sub-1V. The DSP consumes only 10 /spl mu/W at 0.9-V single supply, and occupies 0.3 mm/sup 2/ with gate count of 10k using 0.18-/spl mu/m CMOS process.

Hirotaka Terai - One of the best experts on this subject based on the ideXlab platform.

  • Scalable implementation of a superconducting nanowire single-photon detector array with a superconducting digital signal processor.
    Optics Express, 2020
    Co-Authors: Masahiro Yabuno, Shigeyuki Miyajima, Shigehito Miki, Hirotaka Terai
    Abstract:

    A two-dimensional single-photon imaging system with high sensitivity and high time resolution is the ultimate camera and useful in a wide range of fields. A superconducting nanowire single-photon detector (SSPD or SNSPD) is one of the best candidates for realizing such an ultimate camera due to its high detection efficiency in a wide spectral range, low dark count rate without after-pulsing, and excellent time resolution. Here we propose a new readout scheme to realize a large-scale imaging array based on SSPD, where a row–column readout architecture is combined with a digital signal processor based on a single-flux-quantum (SFQ) circuit. A 16-pixel row–column readout SSPD array is fabricated and measured with an SFQ digital signal processor. We successfully acquired spatial information as encoded digital bit codes with the temporal information of the photon detection. The system timing jitter was measured as

Fangfei Chang - One of the best experts on this subject based on the ideXlab platform.

  • An online emission spectral tomography system with digital signal processor.
    Optics express, 2009
    Co-Authors: Xiong Wan, Wenlin Xiong, Zhimin Zhang, Fangfei Chang
    Abstract:

    Emission spectral tomography (EST) has been adopted to test the three-dimensional distribution parameters of fluid fields, such as burning gas, flame and plasma etc. In most cases, emission spectral data received by the video cameras are enormous so that the emission spectral tomography calculation is often time-consuming. Hence, accelerating calculation becomes the chief factor that one must consider for the practical application of EST. To solve the problem, a hardware implementation method was proposed in this paper, which adopted a digital signal processor (DSP) DM642 in an emission spectral tomography test system. The EST algorithm was fulfilled in the DSP, then calculation results were transmitted to the main computer via the user datagram protocol. Compared with purely VC++ software implementations, this new approach can decrease the calculation time significantly.

Alois Dipl.-ing. Rainer - One of the best experts on this subject based on the ideXlab platform.

  • ICASSP - Adder-based digital signal processor architecture for 80 NS cycle time
    ICASSP '84. IEEE International Conference on Acoustics Speech and Signal Processing, 1
    Co-Authors: Alois Dipl.-ing. Rainer, W. Ulbrich, Lajos Gazsi
    Abstract:

    Architecture and performance tests of a digital signal processor with the following specific features are presented: Short cycle time of 80 ns, shift & add 2's complement arithmetic with saturation and sign-magnitude truncation operations, distributed memories with sophisticated address arithmetics, three stage pipelining, 16 bit instruction format, 20 bit internal data wordlength. In addition to standard problems sophisticated signal processing algorithms (wave digital filtering, Bergland's real-valued FFT, etc.) can powerfully be exploited. Furthermore, this concept is well-suited for implementing multiprocessor configurations.