The Experts below are selected from a list of 4640457 Experts worldwide ranked by ideXlab platform
Gabriel M. Rebeiz - One of the best experts on this subject based on the ideXlab platform.
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interwoven feeding networks with aperture sinc distribution for limited scan phased arrays and reduced number of phase Shifters
IEEE Transactions on Antennas and Propagation, 2018Co-Authors: Bilgehan Avser, Richard F Frazita, Gabriel M. RebeizAbstract:A phased-array feeding network that scans a limited region in space with low-sidelobe levels and a low number of phase Shifters is investigated. The interwoven coupling network is composed of power dividers, couplers, and resistive attenuators with each phase shifter feeding all of the antennas and creating a sinc-like current distribution over the array. This results in a boxcar function-like element pattern and suppresses the grating lobes. The width of the scan region is controlled by the interelement spacing and the coupling and attenuation coefficients of the interwoven network. Different configurations along with theoretical limitations are investigated to determine the scanable region, sidelobe level, and power loss. Two prototype linear arrays with 28 elements are fabricated at 7.9 GHz. The first array employs 14 phase Shifters, has a half power beamwidth (HPBW) of 4°, and can scan up to ±24° with sidelobe levels less than −15 dB. The second array uses seven phase Shifters, has an HPBW of 4°, and can scan up to ±11° with sidelobe levels less than −15 dB. Both of these arrays show state-of-the-art performance in terms of reducing the number of phase Shifters while resulting in low sidelobe levels over the entire scan region.
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0.13-$\mu$m CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Gabriel M. RebeizAbstract:Two 4-bit active phase Shifters integrated with all digital control circuitry in 0.13-mum RF CMOS technology are developed for X- and Ku-band (8-18 GHz) and K-band (18-26 GHz) phased arrays, respectively. The active digital phase Shifters synthesize the required phase using a phase interpolation process by adding quadrature-phased input signals. The designs are based on a resonance-based quadrature all-pass filter for quadrature signaling with minimum loss and wide operation bandwidth. Both phase Shifters can change phases with less than about 2 dB of RMS amplitude imbalance for all phase states through an associated DAC control. For the X- and Ku-band phase shifter, the RMS phase error is less than 10o over the entire 5-18 GHz range. The average insertion loss ranges from to at 5-20 GHz. The input for all 4-bit phase states is typically at -5.4 plusmn1.3 GHz in the X- and Ku-band phase shifter. The K-band phase shifter exhibits 6.5-13 of RMS phase error at 15-26 GHz. The average insertion loss is from 4.6 to at 15-26 GHz. The input of the K-band phase shifter is at 24 GHz. For both phase Shifters, the core size excluding all the pads and the output 50 Omega matching circuits, inserted for measurement purpose only, is very small, 0.33times0.43 mm2 . The total current consumption is 5.8 mA in the X- and Ku-band phase shifter and 7.8 mA in the K-band phase shifter, from a 1.5 V supply voltage.
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Distributed 2- and 3-Bit W-Band MEMS Phase Shifters on Glass Substrates
IEEE Transactions on Microwave Theory and Techniques, 2004Co-Authors: Juo Jung Hung, Laurent Dussopt, Gabriel M. RebeizAbstract:This paper presents state-of-the-art RF microelectromechanical (MEMS) phase Shifters at 75-110 GHz based on the distributed microelectromechanical transmission-line (DMTL) concept. A 3-bit DMTL phase shifter, fabricated on a glass substrate using MEMS switches and coplanar-waveguide lines, results in an average loss of 2.7 dB at 78 GHz (0.9 dB/bit). The measured figure-of-merit performance is 93°/dB-100°/dB (equivalent to 0.9 dB/bit) of loss at 75-110 GHz. The associated phase error is ±3° (rms phase error is 1.56°) and the reflection loss is below -10 dB over all eight states. A 2-bit phase shifter is also demonstrated with comparable performance to the 3-bit design. It is seen that the phase shifter can be accurately modeled using a combination of full-wave electromagnetic and microwave circuit analysis, thereby making the design quite easy up to 110 GHz. These results represent the best phase-shifter performance to date using any technology at W-band frequencies. Careful analysis indicates that the 75-110-GHz figure-of-merit performance becomes 150°/dB-200°/dB, and the 3-bit average insertion loss improves to 1.8-2.1 dB if the phase shifter is fabricated on quartz substrates.
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Optimization of distributed MEMS transmission-line phase Shifters-U-band and W-band designs
IEEE Transactions on Microwave Theory and Techniques, 2000Co-Authors: N. Scott Barker, Gabriel M. RebeizAbstract:The design and optimization of distributed micromechanical system (MEMS) transmission-line phase Shifters at both U- and W-band is presented in this paper. The phase Shifters are fabricated on 500 μm quartz with a center conductor thickness of 8000 Å of gold. The U-band design results in 70°/dB at 40 GHz and 90°/dB at 60 GHz with a 17% change in the MEMS bridge capacitance. The W-band design results in 70°/dB from 75 to 110 GHz with a 15% change in the MEMS bridge capacitance. The W-band phase-shifter performance is limited by the series resistance of the MEMS bridge, which is estimated to be 0.15 Ω. Calculations demonstrate that the performance of the distributed MEMS phase shifter can be greatly increased if the change in the MEMS bridge capacitance can be increased to 30% or 50%. To our knowledge, these results present the best published performance at 60 and 75-110 GHz of any nonwaveguide-based phase shifter.
Yunpeng Lyu - One of the best experts on this subject based on the ideXlab platform.
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schiffman phase Shifters with wide phase shift range under operation of first and second phase periods in a coupled line
IEEE Transactions on Microwave Theory and Techniques, 2020Co-Authors: Leilei Qiu, Lei Zhu, Yunpeng LyuAbstract:In this article, a class of improved Schiffman phase Shifters with two C-section coupled lines separately operating in the first and second phase periods is presented and analyzed. Theoretical model and closed-form synthesis formulae are utilized to analyze the phase performances of the proposed phase Shifters, which reveals significant differences compared to the phase Shifters solely operating in the first or second phase period. Compared to the traditional counterparts, the proposed phase Shifters can achieve a larger phase shift value and a wider phase shift range at the same impedance ratio. Moreover, under the same impedance ratio, the phase shifter can obtain wider phase shift bandwidth. These features are believed to be very useful in the limitedly realizable coupling strength for a wide phase shift range case. Finally, two sets of comparative experiments, including the operations in the first phase period, second phase period, and the proposed type, are designed and fabricated to validate the proposed approach. The simulated and measured results agree well with the theory and achieve a 33.6% (36.7%) increase in phase shift bandwidth when the phase shift value is 90° (150°) under the impedance ratio of 1.5822 (2.0312).
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proposal and synthesis design of differential phase Shifters with filtering function
IEEE Transactions on Microwave Theory and Techniques, 2017Co-Authors: Yunpeng Lyu, Lei Zhu, Chonghu ChengAbstract:In this paper, a new class of filtering differential phase Shifters is proposed and developed, which can provide constant phase shift and self-embedded filtering function at the same time. In contrast to its traditional counterparts, the proposed phase shifter consists of two bandpass filter (BPF) branches and the phase properties of generalized ${n}$ th-order BPF network are systematically studied at first time. With derived closed-form formula of phase slope, the synthesis method is presented to design the proposed filtering differential phase Shifters with prescribed arbitrary phase shift value, passband ripple, and bandwidth. The filter order, which dominates frequency selectivity, is considered in the synthesis design of proposed phase shifter as well. The tradeoff between the frequency selectivity and phase shift is discussed. In addition to the advanced features of multifunction and simple geometry, the proposed filtering differential phase Shifters can achieve compact size, low amplitude imbalance, and multiway polyphase capability. To validate the proposed concept and synthesis method, two filtering differential phase Shifters with single-phase (90°) and five-way polyphase (45°, 90°, 135°, and 180°) are designed, fabricated, and measured. The simulated and measured results coincide well with the prescribed performances in phase shift and magnitude.
Bernard H Stark - One of the best experts on this subject based on the ideXlab platform.
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a new design technique for sub nanosecond delay and 200 v ns power supply slew tolerant floating voltage level Shifters for gan smps
IEEE Transactions on Circuits and Systems I-regular Papers, 2019Co-Authors: Dawei Liu, Simon J Hollis, Bernard H StarkAbstract:Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level Shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level Shifters that deliver slew-rate immunities above 100 V/ns and sub-ns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/( $\mu $ mV), which is an $1.7\times $ improvement on the next best reported level shifter for this type of application.
J Munoz - One of the best experts on this subject based on the ideXlab platform.
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phase shifter placement in large scale systems via mixed integer linear programming
IEEE Transactions on Power Systems, 2003Co-Authors: F G M Lima, F D Galiana, Ivana Kockar, J MunozAbstract:This paper makes use of advances in mixed integer linear programming (MILP) to conduct a preliminary design study on the combinatorial optimal placement of thyristor controlled phase shifter transformers (TCPSTs) in large-scale power systems. The procedure finds the number, network location, and settings of phase Shifters that maximize system loadability under the DC load flow model, subject to limits on the installation investment or total number of TCPSTs. It also accounts for active flow and generation limits, and phase shifter constraints. Simulation results are presented for the IEEE 24-, 118-, and 300-bus systems, as well as a 904-bus network. The principal characteristics of our approach are compared with those of other published flexible AC system transmission (FACTS) allocation methods.
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phase shifter placement in large scale systems via mixed integer linear programming
IEEE Transactions on Power Systems, 2003Co-Authors: F G M Lima, F D Galiana, Ivana Kockar, J MunozAbstract:This paper makes use of advances in mixed integer linear programming (MILP) to conduct a preliminary design study on the combinatorial optimal placement of thyristor controlled phase shifter transformers (TCPSTs) in large-scale power systems. The procedure finds the number, network location, and settings of phase Shifters that maximize system loadability under the DC load flow model, subject to limits on the installation investment or total number of TCPSTs. It also accounts for active flow and generation limits, and phase shifter constraints. Simulation results are presented for the IEEE 24-, 118-, and 300-bus systems, as well as a 904-bus network. The principal characteristics of our approach are compared with those of other published flexible AC system transmission (FACTS) allocation methods.
H.m. Roopashree - One of the best experts on this subject based on the ideXlab platform.
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VLSI Design - A Robust Level-Shifter Design for Adaptive Voltage Scaling
21st International Conference on VLSI Design (VLSID 2008), 2008Co-Authors: Ankur Gupta, Vinod Menezes, Vikas Narang, Rajat Chauhan, H.m. RoopashreeAbstract:Voltage scaling is one of the knobs that is used today to control both static and the active power for SoCs. The SoC core supply voltage is scaled adaptively based on the performance needs. But it is also required to maintain the external electrical chip interface protocol, which may run at a different voltage level. The chip interfaces need to operate reliably under adaptively scaling core voltage and fixed 10 supply voltage. Within the 10 circuits, voltage level Shifters are used to communicate between two voltage domains. This paper examines the performance of a conventional voltage level shifter and describes a novel high performance level shifter that is more robust under adapting voltage scaling.
