The Experts below are selected from a list of 3030 Experts worldwide ranked by ideXlab platform
Ullrich R. Pfeiffer - One of the best experts on this subject based on the ideXlab platform.
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wcdma Direct Conversion Receiver front end comparison in rf cmos and sige bicmos
IEEE Transactions on Microwave Theory and Techniques, 2005Co-Authors: Brian Floyd, Scott K. Reynolds, Thomas Zwick, Lunal Khuon, T Beukema, Ullrich R. PfeifferAbstract:Wide-band code-division multiple-access Direct-Conversion Receiver front-ends have been implemented in both 0.25-/spl mu/m RF-CMOS and SiGe BiCMOS technologies. These circuits have been designed for the same application, radio architecture, and system specifications, allowing relevant comparisons to be made. The front-ends include a bypassable low-noise amplifier, a quadrature downconverter, baseband variable-gain amplifiers, and a local-oscillator frequency divider with output buffers. At 24.5 mA of total current consumption from a 2.7-3.3-V supply, the CMOS front-end has a noise figure of 5.3 dB, in-band third-order intercept point (IIP3) and second-order intercept point (IIP2) of -14 and +20.7 dBm, respectively, and out-of-band IIP3 and IIP2 of >+1.2 and +69 dBm, respectively. Compared to an SiGe front-end consuming 22 mA, the CMOS circuit has a 2-dB higher noise figure, comparable out-of-band linearity, 3-dB higher in-band IIP3, 12-dB lower in-band IIP2, and 7-dB higher LO-to-RF leakage.
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a Direct Conversion Receiver integrated circuit for wcdma mobile systems
Ibm Journal of Research and Development, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype of a 3-V SiGe Direct-Conversion Receiver integrated circuit for use in third-generation (3G) WCDMA mobile cellular systems has been completed. The goal of its design was to minimize current draw while meeting WCDMA Receiver rf specifications with margin. The design includes a bypassable low-noise amplifier, quadrature downconverter, and first-stage variable-gain baseband amplifiers integrated on chip. The design is optimized for use with a single-ended off-chip bandpass surface-acoustic-wave filter with no external matching components. The prototype design represents a first step toward a fully integrated monolithic WCDMA/UMTS Receiver system-on-a-chip. A rigorous set of performance tests are used to characterize the noise and linearity performance of the packaged IC across its full frequency band of operation. A Receiver test-bed system with a software baseband demodulator is used to determine the bit-error-rate performance of the Receiver integrated circuit (IC) at sensitivity. Measured results are compared with estimated system performance requirements to determine compliance with key WCDMA rf specifications.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
IEEE Journal of Solid-State Circuits, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7-3.3-V 14.5-mA SiGe Direct-Conversion Receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
Proceedings of the Bipolar BiCMOS Circuits and Technology Meeting, 1Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7 V, 14.5 mA SiGe Direct-Conversion Receiver IC for use in 3G WCDMA mobile cellular systems has been completed and measured. The design includes a bypassable LNA, a quadrature downconverter, and variable gain baseband amplifiers integrated on chip. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.
Aarno Parssinen - One of the best experts on this subject based on the ideXlab platform.
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a 1 2 v rf front end with on chip vco for pcs 1900 Direct Conversion Receiver in 0 13 spl mu m cmos
IEEE Journal of Solid-state Circuits, 2006Co-Authors: P Sivonen, J Tervaluoto, N Mikkola, Aarno ParssinenAbstract:In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) Direct Conversion Receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downConversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.
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a 22 ma 3 0 db nf Direct Conversion Receiver for 3g wcdma
International Solid-State Circuits Conference, 2001Co-Authors: J. Jussila, Jussi Ryynanen, Aarno Parssinen, L Sumanen, K Kivakas, K HaionenAbstract:A 2-GHz single-chip Direct Conversion Receiver achieves a 3.0-dB double-sideband noise figure, -14-dBm IIP3 and +17-dBm IIP2 with 60-mW power consumption from a 2.7-V supply. The Receiver is targeted for the third generation UTRA/FDD WCDMA system. The low power consumption has been achieved with a proper partitioning and by avoiding buffering between blocks. In the differential RF front end, current boosted quadrature mixers follow the variable-gain low-noise amplifier. At the baseband, on-chip ac-coupled highpass filters are utilized to implement amplification with variable gain having small transients related to gain steps. The outputs of the analog channel selection filters are sampled Directly by the two single-amplifier 6-bit pipeline A/D converters. The spurious tones due to the feedthrough of clock harmonics to the RF input increase the noise figure less than 0.1 dB. The Receiver has been fabricated with a 0.35-/spl mu/m 45-GHz f/sub T/ SiGe BiCMOS process.
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A channel selection filter for a WCDMA Direct Conversion Receiver
2000Co-Authors: J. Jussila, Aarno Parssinen, Kari HalonenAbstract:A channel selection filter for a WCDMA Direct Conversion Receiver is described. The 5th order Chebyshev low-pass filter with a 0.01dB ripple has the -3dB frequency close to 2MHz. The circuit uses two on-chip high-pass filters for offset compensation. The real pole of the prototype is realized with a passive RC element which is the first stage in the filter. The filter achieves +25dBV out-of-band IIP3, + 77dBV out-of-band IIP2 and 9.4nV/√Hz input-referred noise density. The maximum gain is 67.7dB and the circuit draws 4.3mA from a 2.7V supply.
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a 2 ghz wide band Direct Conversion Receiver for wcdma applications
International Solid-State Circuits Conference, 1999Co-Authors: Aarno Parssinen, Jussi Ryynanen, J. Jussila, L Sumanen, Kari HalonenAbstract:A 2-GHz Direct Conversion Receiver for third-generation mobile communications using wide-band code division multiple access achieves -114-dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate. The Receiver is distributed on four dies. The active RC channel selection filter can be programmed to three different bandwidths from 5 to 20-MHz radio-frequency (RF) spacing; and the gain control is merged with filtering. RF and baseband chips use a 25-GHz, 0.3-/spl mu/m BiCMOS technology while the two analog-to-digital converters are implemented with a 0.5-/spl mu/m CMOS. The double-sideband noise figure is 5.1 dB at the 94-dB maximum voltage gain, and the IIP3 and ITP2 are -9.5 and +38 dBm, respectively, The Receiver draws 128 mA from a 2.7-V supply.
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An analog baseband circuitry for a WCDMA Direct Conversion Receiver
1999Co-Authors: J. Jussila, Aarno Parssinen, Kari HalonenAbstract:An analog baseband circuitry for a WCDMA Direct Conversion Receiver is described. The circuitry includes a channel selection filtering and amplification with an adjustable gain in a merged manner. The active RC technique is applied. The filter bandwidth can be set to 2MHz, 4MHz or 8MHz and the gain can be controlled from -9dB to 69dB in 3dB steps. The filter frequency response is tuned with binary weighted switchable capacitor matrices. At the 2MHz bandwidth the chip consumes 39mA from a 2.7V supply. The chip has been fabricated with a 0.35µm BiCMOS process.
Scott K. Reynolds - One of the best experts on this subject based on the ideXlab platform.
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wcdma Direct Conversion Receiver front end comparison in rf cmos and sige bicmos
IEEE Transactions on Microwave Theory and Techniques, 2005Co-Authors: Brian Floyd, Scott K. Reynolds, Thomas Zwick, Lunal Khuon, T Beukema, Ullrich R. PfeifferAbstract:Wide-band code-division multiple-access Direct-Conversion Receiver front-ends have been implemented in both 0.25-/spl mu/m RF-CMOS and SiGe BiCMOS technologies. These circuits have been designed for the same application, radio architecture, and system specifications, allowing relevant comparisons to be made. The front-ends include a bypassable low-noise amplifier, a quadrature downconverter, baseband variable-gain amplifiers, and a local-oscillator frequency divider with output buffers. At 24.5 mA of total current consumption from a 2.7-3.3-V supply, the CMOS front-end has a noise figure of 5.3 dB, in-band third-order intercept point (IIP3) and second-order intercept point (IIP2) of -14 and +20.7 dBm, respectively, and out-of-band IIP3 and IIP2 of >+1.2 and +69 dBm, respectively. Compared to an SiGe front-end consuming 22 mA, the CMOS circuit has a 2-dB higher noise figure, comparable out-of-band linearity, 3-dB higher in-band IIP3, 12-dB lower in-band IIP2, and 7-dB higher LO-to-RF leakage.
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a Direct Conversion Receiver integrated circuit for wcdma mobile systems
Ibm Journal of Research and Development, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype of a 3-V SiGe Direct-Conversion Receiver integrated circuit for use in third-generation (3G) WCDMA mobile cellular systems has been completed. The goal of its design was to minimize current draw while meeting WCDMA Receiver rf specifications with margin. The design includes a bypassable low-noise amplifier, quadrature downconverter, and first-stage variable-gain baseband amplifiers integrated on chip. The design is optimized for use with a single-ended off-chip bandpass surface-acoustic-wave filter with no external matching components. The prototype design represents a first step toward a fully integrated monolithic WCDMA/UMTS Receiver system-on-a-chip. A rigorous set of performance tests are used to characterize the noise and linearity performance of the packaged IC across its full frequency band of operation. A Receiver test-bed system with a software baseband demodulator is used to determine the bit-error-rate performance of the Receiver integrated circuit (IC) at sensitivity. Measured results are compared with estimated system performance requirements to determine compliance with key WCDMA rf specifications.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
IEEE Journal of Solid-State Circuits, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7-3.3-V 14.5-mA SiGe Direct-Conversion Receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
Proceedings of the Bipolar BiCMOS Circuits and Technology Meeting, 1Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7 V, 14.5 mA SiGe Direct-Conversion Receiver IC for use in 3G WCDMA mobile cellular systems has been completed and measured. The design includes a bypassable LNA, a quadrature downconverter, and variable gain baseband amplifiers integrated on chip. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.
Brian Floyd - One of the best experts on this subject based on the ideXlab platform.
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wcdma Direct Conversion Receiver front end comparison in rf cmos and sige bicmos
IEEE Transactions on Microwave Theory and Techniques, 2005Co-Authors: Brian Floyd, Scott K. Reynolds, Thomas Zwick, Lunal Khuon, T Beukema, Ullrich R. PfeifferAbstract:Wide-band code-division multiple-access Direct-Conversion Receiver front-ends have been implemented in both 0.25-/spl mu/m RF-CMOS and SiGe BiCMOS technologies. These circuits have been designed for the same application, radio architecture, and system specifications, allowing relevant comparisons to be made. The front-ends include a bypassable low-noise amplifier, a quadrature downconverter, baseband variable-gain amplifiers, and a local-oscillator frequency divider with output buffers. At 24.5 mA of total current consumption from a 2.7-3.3-V supply, the CMOS front-end has a noise figure of 5.3 dB, in-band third-order intercept point (IIP3) and second-order intercept point (IIP2) of -14 and +20.7 dBm, respectively, and out-of-band IIP3 and IIP2 of >+1.2 and +69 dBm, respectively. Compared to an SiGe front-end consuming 22 mA, the CMOS circuit has a 2-dB higher noise figure, comparable out-of-band linearity, 3-dB higher in-band IIP3, 12-dB lower in-band IIP2, and 7-dB higher LO-to-RF leakage.
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a Direct Conversion Receiver integrated circuit for wcdma mobile systems
Ibm Journal of Research and Development, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype of a 3-V SiGe Direct-Conversion Receiver integrated circuit for use in third-generation (3G) WCDMA mobile cellular systems has been completed. The goal of its design was to minimize current draw while meeting WCDMA Receiver rf specifications with margin. The design includes a bypassable low-noise amplifier, quadrature downconverter, and first-stage variable-gain baseband amplifiers integrated on chip. The design is optimized for use with a single-ended off-chip bandpass surface-acoustic-wave filter with no external matching components. The prototype design represents a first step toward a fully integrated monolithic WCDMA/UMTS Receiver system-on-a-chip. A rigorous set of performance tests are used to characterize the noise and linearity performance of the packaged IC across its full frequency band of operation. A Receiver test-bed system with a software baseband demodulator is used to determine the bit-error-rate performance of the Receiver integrated circuit (IC) at sensitivity. Measured results are compared with estimated system performance requirements to determine compliance with key WCDMA rf specifications.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
IEEE Journal of Solid-State Circuits, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7-3.3-V 14.5-mA SiGe Direct-Conversion Receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
Proceedings of the Bipolar BiCMOS Circuits and Technology Meeting, 1Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7 V, 14.5 mA SiGe Direct-Conversion Receiver IC for use in 3G WCDMA mobile cellular systems has been completed and measured. The design includes a bypassable LNA, a quadrature downconverter, and variable gain baseband amplifiers integrated on chip. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.
Herschel A. Ainspan - One of the best experts on this subject based on the ideXlab platform.
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a Direct Conversion Receiver integrated circuit for wcdma mobile systems
Ibm Journal of Research and Development, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype of a 3-V SiGe Direct-Conversion Receiver integrated circuit for use in third-generation (3G) WCDMA mobile cellular systems has been completed. The goal of its design was to minimize current draw while meeting WCDMA Receiver rf specifications with margin. The design includes a bypassable low-noise amplifier, quadrature downconverter, and first-stage variable-gain baseband amplifiers integrated on chip. The design is optimized for use with a single-ended off-chip bandpass surface-acoustic-wave filter with no external matching components. The prototype design represents a first step toward a fully integrated monolithic WCDMA/UMTS Receiver system-on-a-chip. A rigorous set of performance tests are used to characterize the noise and linearity performance of the packaged IC across its full frequency band of operation. A Receiver test-bed system with a software baseband demodulator is used to determine the bit-error-rate performance of the Receiver integrated circuit (IC) at sensitivity. Measured results are compared with estimated system performance requirements to determine compliance with key WCDMA rf specifications.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
IEEE Journal of Solid-State Circuits, 2003Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7-3.3-V 14.5-mA SiGe Direct-Conversion Receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.
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A Direct-Conversion Receiver IC for WCDMA mobile systems
Proceedings of the Bipolar BiCMOS Circuits and Technology Meeting, 1Co-Authors: Scott K. Reynolds, Brian Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. AinspanAbstract:A prototype design of a 2.7 V, 14.5 mA SiGe Direct-Conversion Receiver IC for use in 3G WCDMA mobile cellular systems has been completed and measured. The design includes a bypassable LNA, a quadrature downconverter, and variable gain baseband amplifiers integrated on chip. The static sensitivity performance of the Receiver IC is characterized using a software baseband processor to compute link bit-error rate.