The Experts below are selected from a list of 2826 Experts worldwide ranked by ideXlab platform

Kari Halonen - One of the best experts on this subject based on the ideXlab platform.

  • Direct Digital Synthesizers theory design and applications
    Direct Digital Synthesizers: Theory Design and Applications 1st, 2010
    Co-Authors: J Vankka, Kari Halonen
    Abstract:

    A major advantage of a Direct Digital Synthesizer is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under Digital processor control. This book was written to find possible applications for radio communication systems.

  • A 1.5-V Direct Digital Synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS
    IEEE Journal of Solid-State Circuits, 2005
    Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari Halonen
    Abstract:

    In Direct Digital Synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current: 11.5 mA).

  • CICC - A 1.5V Direct Digital Synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
    Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004
    Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari Halonen
    Abstract:

    In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the Direct Digital Synthesizer (DDS) output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current 11.5 mA).

  • A Direct Digital Synthesizer with Tunable Delta Sigma Modulator
    Analog Integrated Circuits and Signal Processing, 2004
    Co-Authors: Jouko Vankka, Jonne Lindeberg, Kari Halonen
    Abstract:

    In Direct Digital Synthesizer (DDS) applications, the drawback of the conventional delta sigma (ΔΣ) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the ΔΣ modulator is tuned according to the DDS output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. Two DDSs with tunable 1-bit ΔΣ D/A converters (real and complex) were designed and implemented on a programmable logic device (PLD); experimental results show their desired operation and performance.

  • ISCAS (1) - Direct Digital Synthesizer with tunable delta sigma modulator
    Analog Integrated Circuits and Signal Processing, 2004
    Co-Authors: Jouko Vankka, Jonne Lindeberg, Kari Halonen
    Abstract:

    In Direct Digital Synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the proposed architecture, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise cubic segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. Two DDSs with tunable 1 bit /spl Delta//spl Sigma/ D/A converters (real and complex) were designed and implemented on a programmable logic device (PLD); experimental results show their desired operation and performance.

Jouko Vankka - One of the best experts on this subject based on the ideXlab platform.

  • A 1.5-V Direct Digital Synthesizer with tunable delta-sigma modulator in 0.13-/spl mu/m CMOS
    IEEE Journal of Solid-State Circuits, 2005
    Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari Halonen
    Abstract:

    In Direct Digital Synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware-efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with 16 equal-length piecewise second-degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with an output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current: 11.5 mA).

  • CICC - A 1.5V Direct Digital Synthesizer with tunable delta sigma modulator in 0.13 /spl mu/m CMOS
    Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571), 2004
    Co-Authors: Jonne Lindeberg, Johan Sommarek, Jouko Vankka, Kari Halonen
    Abstract:

    In the new architecture presented in this paper, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the Direct Digital Synthesizer (DDS) output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise-continuous second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. The die area of the chip is 2.02 mm/sup 2/ (0.13 /spl mu/m CMOS technology). The total power consumption is 138 mW at 1.5 V with output frequency of 63.33 MHz at a clock frequency of 200 MHz (D/A converter full-scale output current 11.5 mA).

  • A Direct Digital Synthesizer with Tunable Delta Sigma Modulator
    Analog Integrated Circuits and Signal Processing, 2004
    Co-Authors: Jouko Vankka, Jonne Lindeberg, Kari Halonen
    Abstract:

    In Direct Digital Synthesizer (DDS) applications, the drawback of the conventional delta sigma (ΔΣ) modulator structure is that its signal band is fixed. In the new architecture presented in this paper, the signal band of the ΔΣ modulator is tuned according to the DDS output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length second degree polynomial segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. Two DDSs with tunable 1-bit ΔΣ D/A converters (real and complex) were designed and implemented on a programmable logic device (PLD); experimental results show their desired operation and performance.

  • ISCAS (1) - Direct Digital Synthesizer with tunable delta sigma modulator
    Analog Integrated Circuits and Signal Processing, 2004
    Co-Authors: Jouko Vankka, Jonne Lindeberg, Kari Halonen
    Abstract:

    In Direct Digital Synthesizer (DDS) applications, the drawback of the conventional delta sigma (/spl Delta//spl Sigma/) modulator structure is that its signal band is fixed. In the proposed architecture, the signal band of the /spl Delta//spl Sigma/ modulator is tuned according to the DDS output frequency. We use a hardware efficient phase-to-sine amplitude converter in the DDS that approximates the first quadrant of the sine function with sixteen equal length piecewise cubic segments. The DDS is capable of frequency, phase, and quadrature amplitude modulation. Two DDSs with tunable 1 bit /spl Delta//spl Sigma/ D/A converters (real and complex) were designed and implemented on a programmable logic device (PLD); experimental results show their desired operation and performance.

  • Direct Digital Synthesizer
    Direct Digital Synthesizers, 2001
    Co-Authors: Jouko Vankka, Kari Halonen
    Abstract:

    In this chapter the operation of the Direct Digital Synthesizer is first described. It is simple to add modulation capabilities to the DDS, because the DDS is a Digital signal processing device. It is shown that the DDS produces spurs as well as the desired output frequency.

Richard C. Jaeger - One of the best experts on this subject based on the ideXlab platform.

  • A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $\mu$m SiGe BiCMOS Technology
    IEEE Journal of Solid-State Circuits, 2008
    Co-Authors: Xuefeng Yu, David J Irwin, Richard C. Jaeger
    Abstract:

    This paper presents a 12 GHz Direct Digital Synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm2. The chip was measured in packaged prototypes using 48-pin ceramic LCC packages.

  • A low power 5 GHz Direct Digital Synthesizer designed in SiGe technology
    Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems 2004., 1
    Co-Authors: Foster Dai, L.s.j. Chimakurthy, D. Yang, J. Huang, Richard C. Jaeger
    Abstract:

    This paper presents a low power high-speed Direct Digital Synthesizer (DDS), designed in a 47 GHz SiGe technology. The ROM-less DDS includes an 8-bit accumulator and an 8 bit cosine-weighted Digital-to-analog converter (DAC) operating at a maximum 5 GHz clock frequency. The DDS core occupies an area of 2 mm/sup 2/ and consumes less than 2 W power with a 3.3 V supply voltage. The 5 GHz MMIC provides a frequency synthesis and modulation means for L-band applications.

Robert Weigel - One of the best experts on this subject based on the ideXlab platform.

  • a differential pair based Direct Digital Synthesizer mmic with 16 8 ghz clock and 488 mw power consumption
    IEEE Transactions on Microwave Theory and Techniques, 2010
    Co-Authors: Benjamin Laemmle, Christoph Wagner, Herbert Knapp, Linus Maurer, Herbert Jaeger, Robert Weigel
    Abstract:

    This paper presents a low-power, high-speed Direct Digital Synthesizer monolithic microwave integrated circuit in a SiGe bipolar technology with 8-bit phase and 6-bit amplitude resolution. The phase-to-amplitude mapping circuit is implemented as a differential pair in saturation. The use of a modern SiGe bipolar technology enables both a low power consumption of 488 mW at a 3.3-V supply and a high clock frequency of 16.8 GHz; here, the maximum output frequency is 8.3344 GHz and the frequency resolution is 65.625 MHz. A spurious-free dynamic range (SFDR) between 47-20 dBc is achieved. First Nyquist zone SFDR, narrowband SFDR, and frequency-modulation measurements of the signal are shown and discussed. The chip is fabricated in a 0.35-?m 200-GHz fT SiGe bipolar technology and occupies only 1128 × 1028 ?m2. The chip is mounted on a printed circuit board for measurement.

  • Temperature calibration of a differential pair based Direct Digital Synthesizer through subsampling spectral analysis
    2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2010
    Co-Authors: Benjamin Laemmle, Christoph Wagner, Herbert Jaeger, Robert Weigel
    Abstract:

    The temperature behavior of a high speed Direct Digital Synthesizer with a maximum clock frequency of 16.8GHz and a power consumption of 488mW at room temperature is investigated. The DDS has been manufactured in a 200-GHz f t SiGe bipolar technology and occupies a chip area of 1.15mm2. A subsampling approach is introduced to analyze the output spectrum of the DDS. A calibration is performed over temperature to improve the spectral performance of the DDS. The calibration is based on a two point measurement and the use of a look-up table. After calibration, the third harmonic is below 53 dBc and a narrow band SFDR is nearly constant at 38 dBc.

  • A 366mW Direct Digital Synthesizer at 15GHz clock frequency in SiGe Bipolar technology
    2009 IEEE Radio Frequency Integrated Circuits Symposium, 2009
    Co-Authors: Benjamin Laemmle, Christoph Wagner, Herbert Knapp, Linus Maurer, Robert Weigel
    Abstract:

    A Direct Digital Synthesizer (DDS) with 6-bit amplitude and 8-bit phase resolution is presented. The phase-to-amplitude mapping circuit is implemented as a differential pair in saturation. The suitability of this circuit for broadband application and high temperature range is shown. The use of a modern SiGe bipolar technology enables both a low power consumption of 366mW and a high clock frequency of 15GHz. A spurious free dynamic range (SFDR) between 42 and 20 dBc is achieved. The chip is fabricated in a 0.35 µm 200-GHz f T SiGe bipolar technology and occupies only 1024×1128 µm2.

David J Irwin - One of the best experts on this subject based on the ideXlab platform.

  • 24 bit 5 0 ghz Direct Digital Synthesizer rfic with Direct Digital modulations in 0 13 mu m sige bicmos technology
    IEEE Journal of Solid-state Circuits, 2010
    Co-Authors: Xueyang Geng, Fa Foster Dai, David J Irwin, R C Jaeger
    Abstract:

    This paper presents a 24-bit 5.0 GHz ultrahigh-speed Direct Digital Synthesizer (DDS) with Direct Digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with Direct Digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for Direct Digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted Digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as Digital-to-analog conversion. The DDS core occupies 3.0 × 2.5 mm2 and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 μm SiGe BiCMOS technology with fT/fMAX = 200/250 GHz and tested in a CLCC-68 package.

  • a 9 bit quadrature Direct Digital Synthesizer implemented in 0 18 mu hbox m sige bicmos technology
    Radio Frequency Integrated Circuits Symposium, 2008
    Co-Authors: Fa Foster Dai, David J Irwin, R C Jaeger
    Abstract:

    This paper describes a 9-bit 6.2-GHz low power quadrature Direct Digital Synthesizer (DDS) implemented in a 0.18-mum SiGe BiCMOS technology. With a 9-bit pipeline accumulator and two 8-bit sine-weighted current steering DACs, this DDS is capable of generating quadrature sinusoidal waveforms up to 3.15 GHz with a maximum clock frequency of 6.2 GHz. Packed with more than 13 500 transistors, the quadrature DDS occupies an active area of 2.3 times 2.5 mm2 and a total die area of 3.0 times 3.0 mm2. The measured spurious-free dynamic range is approximately 26 dBc at a clock frequency 6.2 GHz. At the maximum clock frequency, the power consumption of the DDS is 2.5 W with 3.3- and 4.0-V power supplies for the Digital and analog parts, respectively. The DDS thus achieves a power efficiency figure-of-merit of 5.04 GHz/W/phase. The DDS chips were packaged with 48-pin ceramic leadless chip carriers and air cooling was used during the measurement.

  • A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 $\mu$m SiGe BiCMOS Technology
    IEEE Journal of Solid-State Circuits, 2008
    Co-Authors: Xuefeng Yu, David J Irwin, Richard C. Jaeger
    Abstract:

    This paper presents a 12 GHz Direct Digital Synthesizer (DDS) MMIC with 9-bit phase and 8-bit amplitude resolution implemented in a 0.18 mum SiGe BiCMOS technology. Composed of a 9-bit pipeline accumulator and an 8-bit sine-weighted current-steering DAC, the DDS is capable of synthesizing sinusoidal waveforms up to 5.93 GHz. The maximum clock frequency of the DDS MMIC is measured as 11.9 GHz at the Nyquist output and 12.3 GHz at 2.31 GHz output. The spurious-free dynamic range (SFDR) of the DDS, measured at Nyquist output with an 11.9 GHz clock, is 22 dBc. The power consumption of the DDS MMIC measured at a 12 GHz clock input is 1.9 W with dual power supplies of 3.3 V/4 V. The DDS thus achieves a record-high power efficiency figure of merit (FOM) of 6.3 GHz/W. With more than 9600 transistors, the active area of the MMIC is only 2.5 x 0.7 mm2. The chip was measured in packaged prototypes using 48-pin ceramic LCC packages.