The Experts below are selected from a list of 8205 Experts worldwide ranked by ideXlab platform
Philippe Molson - One of the best experts on this subject based on the ideXlab platform.
-
automated generation of hardware accelerators with direct memory access from ansi iso standard c functions
Field-Programmable Custom Computing Machines, 2006Co-Authors: Orion Pritchard, Philippe MolsonAbstract:Methodologies for synthesis of stand-alone hardware modules from C/C++ based languages have been gaining adoption for embedded system design, as an essential means to stay ahead of increasing performance, complexity, and time-to-market demands. However, using C to generate stand-alone blocks does not allow for truly seamless unification of embedded software and hardware development flows. This paper describes a methodology for generating hardware accelerator modules that are tightly coupled with a soft RISC CPU, its tool chain, and its memory system. This coupling allows for several significant advancements: (1) a unified development environment with true pushbutton switching between original software and hardware-accelerated implementations, (2) direct access to memory from the accelerator module, (3) full support for pointers and arrays, and (4) latency-aware pipelining of memory transactions. We also present results of our implementation, the C2H compiler. Eight user test cases on common embedded applications show speedup factors of 13x-73x achieved in less than a few days
-
automated generation of hardware accelerators with direct memory access from ansi iso standard c functions
Field-Programmable Custom Computing Machines, 2006Co-Authors: Orion Pritchard, Philippe MolsonAbstract:Methodologies for synthesis of stand-alone hardware modules from C/C++ based languages have been gaining adoption for embedded system design, as an essential means to stay ahead of increasing performance, complexity, and time-to-market demands. However, using C to generate stand-alone blocks does not allow for truly seamless unification of embedded software and hardware development flows. This paper describes a methodology for generating hardware accelerator modules that are tightly coupled with a soft RISC CPU, its tool chain, and its memory system. This coupling allows for several significant advancements: (1) a unified development environment with true pushbutton switching between original software and hardware-accelerated implementations, (2) direct access to memory from the accelerator module, (3) full support for pointers and arrays, and (4) latency-aware pipelining of memory transactions. We also present results of our implementation, the C2H compiler. Eight user test cases on common embedded applications show speedup factors of 13x-73x achieved in less than a few days
Orion Pritchard - One of the best experts on this subject based on the ideXlab platform.
-
automated generation of hardware accelerators with direct memory access from ansi iso standard c functions
Field-Programmable Custom Computing Machines, 2006Co-Authors: Orion Pritchard, Philippe MolsonAbstract:Methodologies for synthesis of stand-alone hardware modules from C/C++ based languages have been gaining adoption for embedded system design, as an essential means to stay ahead of increasing performance, complexity, and time-to-market demands. However, using C to generate stand-alone blocks does not allow for truly seamless unification of embedded software and hardware development flows. This paper describes a methodology for generating hardware accelerator modules that are tightly coupled with a soft RISC CPU, its tool chain, and its memory system. This coupling allows for several significant advancements: (1) a unified development environment with true pushbutton switching between original software and hardware-accelerated implementations, (2) direct access to memory from the accelerator module, (3) full support for pointers and arrays, and (4) latency-aware pipelining of memory transactions. We also present results of our implementation, the C2H compiler. Eight user test cases on common embedded applications show speedup factors of 13x-73x achieved in less than a few days
-
automated generation of hardware accelerators with direct memory access from ansi iso standard c functions
Field-Programmable Custom Computing Machines, 2006Co-Authors: Orion Pritchard, Philippe MolsonAbstract:Methodologies for synthesis of stand-alone hardware modules from C/C++ based languages have been gaining adoption for embedded system design, as an essential means to stay ahead of increasing performance, complexity, and time-to-market demands. However, using C to generate stand-alone blocks does not allow for truly seamless unification of embedded software and hardware development flows. This paper describes a methodology for generating hardware accelerator modules that are tightly coupled with a soft RISC CPU, its tool chain, and its memory system. This coupling allows for several significant advancements: (1) a unified development environment with true pushbutton switching between original software and hardware-accelerated implementations, (2) direct access to memory from the accelerator module, (3) full support for pointers and arrays, and (4) latency-aware pipelining of memory transactions. We also present results of our implementation, the C2H compiler. Eight user test cases on common embedded applications show speedup factors of 13x-73x achieved in less than a few days
Ling Shao - One of the best experts on this subject based on the ideXlab platform.
-
automatic loop tiling for direct memory access
International Parallel and Distributed Processing Symposium, 2011Co-Authors: Haibo Lin, Tao Liu, Tong Chen, Lakshminarayanan Renganarayana, Kevin Obrien, Ling ShaoAbstract:In heterogeneous multi-core systems, such as the Cell BE processor, each accelerator core has its own fast local memory without hardware supported coherence and the software is responsible to dynamically transfer data between the fast local and slow global memory. The data can be transferred through either a software controlled cache or a direct buffer. The software controlled cache maintains correctness for arbitrary access patterns, but introduces the extra overhead of cache lookup. direct buffer is efficient for regular accesses, while requiring precise analysis, detailed modeling of execution, and significant code generation. In this paper we present the design and implementation of {\em DMATiler} which combines compiler analysis and runtime management to optimize local memory performance via automatic loop tiling and buffer optimization techniques. The DMATiler chooses a data transfer friendly loop order and using a empirically validated DMA performance model, it formulates and solves a convex optimization problem to determine globally optimal tile sizes. Further, the DMATiler applies optimization techniques such compressed data transfers and DMA commands to achieve the best DMA performance for a given loop nest. We have implemented the DMATiler in the IBM XL Single Source Compiler (SSC), and have conducted experiments with a set of loop nest benchmarks. The results show that the DMATiler is much more efficient than software controlled cache (average speedup of 9.8x) and single level loop blocking (average speedup of 6.2x) on the Cell BE processor.
-
dmatiler revisiting loop tiling for direct memory access
International Conference on Parallel Architectures and Compilation Techniques, 2010Co-Authors: Haibo Lin, Tao Liu, Tong Chen, Lakshminarayanan Renganarayana, John Kevin Patrick Obrien, Ling ShaoAbstract:In this paper we present the design and implementation of a DMATiler which combines compiler analysis and runtime management to optimize local memory performance. In traditional cache model based loop tiling optimizations, the compiler approximates runtime cache misses as the number of distinct cache lines touched by a loop nest. In contrast, the DMATiler has the full control of the addresses, sizes, and sequences of data transfers. DMATiler uses a simplified DMA performance model to formulate the cost model for DMA-tiled loop nests, then solves it using a custom gradient descent algorithm with heuristics guided by DMA characteristics. Given a loop nest, DMATiler uses loop interchange to make the loop order more friendlier for data movements. Moreover, DMATiler applies compressed data buffer and advanced DMA command to further optimize data transfers. We have implemented the DMATiler in the IBM XL C/C++ for Multi-core Acceleration for Linux, and have conducted experiments with a set of loop nest benchmarks. The results show DMATiler is much more efficient than software controlled cache (average speedup of 9.8x) and single level loop blocking (average speedup of 6.2x) on the Cell BE processor.
Haibo Lin - One of the best experts on this subject based on the ideXlab platform.
-
automatic loop tiling for direct memory access
International Parallel and Distributed Processing Symposium, 2011Co-Authors: Haibo Lin, Tao Liu, Tong Chen, Lakshminarayanan Renganarayana, Kevin Obrien, Ling ShaoAbstract:In heterogeneous multi-core systems, such as the Cell BE processor, each accelerator core has its own fast local memory without hardware supported coherence and the software is responsible to dynamically transfer data between the fast local and slow global memory. The data can be transferred through either a software controlled cache or a direct buffer. The software controlled cache maintains correctness for arbitrary access patterns, but introduces the extra overhead of cache lookup. direct buffer is efficient for regular accesses, while requiring precise analysis, detailed modeling of execution, and significant code generation. In this paper we present the design and implementation of {\em DMATiler} which combines compiler analysis and runtime management to optimize local memory performance via automatic loop tiling and buffer optimization techniques. The DMATiler chooses a data transfer friendly loop order and using a empirically validated DMA performance model, it formulates and solves a convex optimization problem to determine globally optimal tile sizes. Further, the DMATiler applies optimization techniques such compressed data transfers and DMA commands to achieve the best DMA performance for a given loop nest. We have implemented the DMATiler in the IBM XL Single Source Compiler (SSC), and have conducted experiments with a set of loop nest benchmarks. The results show that the DMATiler is much more efficient than software controlled cache (average speedup of 9.8x) and single level loop blocking (average speedup of 6.2x) on the Cell BE processor.
-
dmatiler revisiting loop tiling for direct memory access
International Conference on Parallel Architectures and Compilation Techniques, 2010Co-Authors: Haibo Lin, Tao Liu, Tong Chen, Lakshminarayanan Renganarayana, John Kevin Patrick Obrien, Ling ShaoAbstract:In this paper we present the design and implementation of a DMATiler which combines compiler analysis and runtime management to optimize local memory performance. In traditional cache model based loop tiling optimizations, the compiler approximates runtime cache misses as the number of distinct cache lines touched by a loop nest. In contrast, the DMATiler has the full control of the addresses, sizes, and sequences of data transfers. DMATiler uses a simplified DMA performance model to formulate the cost model for DMA-tiled loop nests, then solves it using a custom gradient descent algorithm with heuristics guided by DMA characteristics. Given a loop nest, DMATiler uses loop interchange to make the loop order more friendlier for data movements. Moreover, DMATiler applies compressed data buffer and advanced DMA command to further optimize data transfers. We have implemented the DMATiler in the IBM XL C/C++ for Multi-core Acceleration for Linux, and have conducted experiments with a set of loop nest benchmarks. The results show DMATiler is much more efficient than software controlled cache (average speedup of 9.8x) and single level loop blocking (average speedup of 6.2x) on the Cell BE processor.
Walter Stechele - One of the best experts on this subject based on the ideXlab platform.
-
A new framework to accelerate Virtex-II Pro dynamic partial selfreconfiguration
2014Co-Authors: Christopher Claus, Florian H. Müller, Walter Stechele, Technische Universität MünchenAbstract:The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconf iguration, also known as dynamic partial reconf iguration (DPR). Taking this concept one step further, partial dynamic self-reconf iguration becomes possible through the Internal Conf iguration access Port (ICAP). In this paper a framework for lowering reconf iguration times using the combitgen tool [2] to reduce the overhead found within bitstreams, along with a completely new, very simple and area eff icient ICAP controller that is connected directly to the Processor Local Bus (PLB) and is equipped with direct memory access (DMA) capabilities is presented. Using this PLB Master ICAP controller, it is possible to reach the maximum practical throughput that can be achieved with the ICAP interface of Virtex-II Pro devices. Compared to an alternative realization using the OPBHWICAP provided by Xilinx (a slave attachment on the On-Chip Peripheral Bus), it is possible to achieve improvements concerning reconf iguration times by a factor of 20
-
a new framework to accelerate virtex ii pro dynamic partial self reconfiguration
International Parallel and Distributed Processing Symposium, 2007Co-Authors: Christopher Claus, Florian H. Müller, J Zeppenfeld, Walter StecheleAbstract:The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one step further, partial dynamic self-reconfiguration becomes possible through the internal configuration access port (ICAP). In this paper a framework for lowering reconfiguration times using the combitgen tool to reduce the overhead found within bitstreams, along with a completely new, very simple and area efficient ICAP controller that is connected directly to the processor local bus (PLB) and is equipped with direct memory access (DMA) capabilities is presented. Using this PLB Master ICAP controller, it is possible to reach the maximum practical throughput that can be achieved with the ICAP interface of Virtex-II Pro devices. Compared to an alternative realization using the OPBHWICAP provided by Xilinx (a slave attachment on the on-chip peripheral bus), it is possible to achieve improvements concerning reconfiguration times by a factor of 20.