Divider

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Behzad Razavi - One of the best experts on this subject based on the ideXlab platform.

  • a 40 ghz frequency Divider in 0 18 spl mu m cmos technology
    IEEE Journal of Solid-state Circuits, 2004
    Co-Authors: Behzad Razavi
    Abstract:

    An analysis of regenerative Dividers predicts the required phase shift or selectivity for proper operation. A Divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

  • A 40-GHz Frequency Divider in 0.18-μm CMOS Technology
    IEEE Journal of Solid-State Circuits, 2004
    Co-Authors: Jri Lee, Behzad Razavi
    Abstract:

    An analysis of regenerative Dividers predicts the required phase shift or selectivity for proper operation. A Divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded ÷2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

  • a 40 ghz frequency Divider in 0 18 spl mu m cmos technology
    Symposium on VLSI Circuits, 2003
    Co-Authors: Behzad Razavi
    Abstract:

    A frequency Divider employs resonance techniques by means of on-chip spiral inductors to operate at high speeds. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

Yongle Wu - One of the best experts on this subject based on the ideXlab platform.

  • an analytical approach for a novel coupled line dual band wilkinson power Divider
    IEEE Transactions on Microwave Theory and Techniques, 2011
    Co-Authors: Yongle Wu
    Abstract:

    A novel generalized coupled-line circuit structure for a dual-band Wilkinson power Divider is proposed. The proposed power Divider is composed of two coupled lines with different even- and odd-mode characteristic impedances and two lumped resistors. Using rigorous even- and odd-mode analysis, the analytical design equations for this proposed power Divider are obtained and the ideal closed-form scattering parameters are constructed. Since the traditional transmission line is a special case of coupled line (coupled coefficient is zero), it is found that traditional noncoupled-line dual-band (including single band) Wilkinson power Dividers and previous dual-band coupled-line power Dividers are special cases of this generalized power Divider. As a typical example, which could only be designed by using this given design equations, a compact microstrip 3-dB power Divider operating at both 1.1 and 2.2 GHz is designed, fabricated, and measured. There is good agreement between calculated and measured results.

  • an unequal dual frequency wilkinson power Divider with optional isolation structure
    Progress in Electromagnetics Research-pier, 2009
    Co-Authors: Yongle Wu, Shulan Li
    Abstract:

    In this paper, we propose a generalized Wilkinson power Divider operating at two arbitrary frequencies with unequal power dividing ratio. To achieve unequal power division and perfect matching at dual-frequency, a novel structure consisted of four dual-frequency transformers in two sections is proposed. For the compact power Divider, the parallel and series RLC structures can be chosen to obtain effective isolation between the two outports according to different frequency ratios. Furthermore, the closed-form design equations of the unequal dual-frequency power Divider are derived based on circuit theory and transmission line theory. Finally, simulation and experiment results of two examples including parallel and series RLC structures indicate that all the theoretical features of these unequal power Dividers can be fulfilled at dual-frequency simultaneously.

A L Lacaita - One of the best experts on this subject based on the ideXlab platform.

  • a 13 5 mw 5 ghz frequency synthesizer with dynamic logic frequency Divider
    IEEE Journal of Solid-state Circuits, 2004
    Co-Authors: S Pellerano, Salvatore Levantino, Carlo Samori, A L Lacaita
    Abstract:

    The adoption of dynamic Dividers in CMOS phase-locked loops for multigigahertz applications allows to reduce the power consumption substantially without impairing the phase noise and the power supply sensitivity of the phase-locked loop (PLL). A 5-GHz frequency synthesizer integrated in a 0.25-/spl mu/m CMOS technology demonstrates a total power consumption of 13.5 mW. The frequency Divider combines the conventional and the extended true-single-phase-clock logics. The oscillator employs a rail-to-rail topology in order to ensure a proper Divider function. This PLL intended for wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in steps of 20 MHz. The reference spurs at 10-MHz offset are as low as -70 dBc and the phase noise is lower than -116 dBc/Hz at 1 MHz over the whole tuning range.

Shingo Okamura - One of the best experts on this subject based on the ideXlab platform.

  • a generalized dual band wilkinson power Divider with parallel l c and r components
    IEEE Transactions on Microwave Theory and Techniques, 2012
    Co-Authors: Xiaolong Wang, U Sakagami, Kensaku Takahashi, Shingo Okamura
    Abstract:

    A generalized model of a two-way dual-band Wilkinson power Divider (WPD) with a parallel LC circuit at midpoints of two-segment transformers is proposed and compared with that of a conventional two-way dual-band WPD with a parallel LC circuit at the ends of two-segment transformers. The sum of power reflected at an output port and power transmitted to an isolation port from another isolation port in the proposed Divider is smaller than that in the conventional Divider. Therefore, wide bandwidths for S22, S33, and S32 can be expected for proposed Dividers. In the case of equal power division, frequency characteristics of return loss at output ports and isolation of the proposed Divider are wider than those of the convention one. The resonant frequencies of LC circuits in the proposed Divider and a conventional Divider are equal; however, the inductance L used in the proposed Divider is always smaller than that in the conventional Divider. Design charts and calculated bandwidths as a function of frequency ratio from 1 to 7 are presented. In experiments, two symmetrical and two asymmetrical circuits were fabricated. The experimental results showed good agreement with theoretical results.

Yi-jan Emery Chen - One of the best experts on this subject based on the ideXlab platform.

  • A W-Band Harmonically Enhanced CMOS Divide-by-Three Frequency Divider
    IEEE Microwave and Wireless Components Letters, 2014
    Co-Authors: Yang-wen Chen, Hugo Cruz, Yi-jan Emery Chen
    Abstract:

    This letter presents a W-band wide-locking range divide-by-three injection-locked frequency Divider (ILFD) implemented in 90 nm digital CMOS technology. The second-harmonic generator (SHG) is proposed to boost the second harmonic signal for effective harmonic mixing and extend the locking range of the frequency Divider. The power consumption of the Divider is 10.8 mW and the operation frequency of the input signal ranges from 73.1 to 84.3 GHz. To the authors' knowledge, this work is the first W-band divide-by-three ILFD with the locking range wider than 10%.

  • a 0 8 mw 55 ghz dual injection locked cmos frequency Divider
    IEEE Transactions on Microwave Theory and Techniques, 2008
    Co-Authors: Yi-jan Emery Chen
    Abstract:

    This paper presents the dual-injection-locking technique to enhance the locking range of resonator-based frequency Dividers. By fully utilizing the voltage and current injection of the input signal, the Divider locking range is extended significantly. The 0.8-mW dual-injection-locked frequency Divider was developed in 90-nm digital CMOS technology. The total chip size is 0.77 mm times 0.5 mm. Without any varactor or inductor tuning, the input signal frequency coverage of the Divider is from 35.7 to 54.9 GHz. Combined with the excellent locking range and sub-milliwatt power consumption, the figure-of-merit of this work surpasses those of the previous resonator-based Dividers by more than one order.