The Experts below are selected from a list of 315 Experts worldwide ranked by ideXlab platform
Reza Fazel-rezai - One of the best experts on this subject based on the ideXlab platform.
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EMBC - Computationally efficient QRS detection analysis based on Dual-Slope method.
Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and, 2014Co-Authors: M. Riadh Arefin, Reza Fazel-rezaiAbstract:This paper presents a computationally efficient QRS detection algorithm for wearable electrocardiogram (ECG) applications based on Dual-Slope analysis. In general, ECG signals of arrhythmias are pseudo-periodic and contaminated with noises like the patient's contraction muscles, respiration, 60 Hz interference and other types which impede correct QRS detection. To resolve this problem, in this paper, a technique is presented which is based on two Slopes on both sides of a peak in ECG signal. Based on these Slopes, a variable measuring steepness is developed and R peaks are detected. The algorithm was evaluated against MIT/BIH arrhythmia database and achieved 99.38% detection rate. This method was compared with one of the recently developed Dual-Slope based QRS detection methods. The results showed that the proposed method has 12.48 times faster runtime than the old method.
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Computationally efficient QRS detection analysis based on Dual-Slope method
2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014Co-Authors: Riadh M. Arefin, Reza Fazel-rezaiAbstract:This paper presents a computationally efficient QRS detection algorithm for wearable electrocardiogram (ECG) applications based on Dual-Slope analysis. In general, ECG signals of arrhythmias are pseudo-periodic and contaminated with noises like the patient's contraction muscles, respiration, 60 Hz interference and other types which impede correct QRS detection. To resolve this problem, in this paper, a technique is presented which is based on two Slopes on both sides of a peak in ECG signal. Based on these Slopes, a variable measuring steepness is developed and R peaks are detected. The algorithm was evaluated against MIT/BIH arrhythmia database and achieved 99.38% detection rate. This method was compared with one of the recently developed Dual-Slope based QRS detection methods. The results showed that the proposed method has 12.48 times faster runtime than the old method.
R. Yusof - One of the best experts on this subject based on the ideXlab platform.
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ISCAS (5) - Performance analysis of online Dual Slope delta modulated PWM inverter
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: R. Razali, V. Subbiah, M.a. Choudhury, R. YusofAbstract:Delta modulation (DM) is a simple pulse width modulation (PWM) scheme especially suitable for AC machine drives where a constant flux operation is desired. However, the modulator has inferior characteristics when compared to conventional sine PWM and therefore it is not normally used. The disadvantages of delta modulators can be significantly reduced by allowing online parameter variation and synchronous operation. This paper attempts to identify the modulation parameters of a delta modulator, which can be varied during constant and variable frequency operation of the three-phase voltage source inverter (VSI) so as to improve the performance in terms of harmonic content and fundamental voltage availability. A new technique of implementing the delta modulator by a microcomputer is proposed. The method is novel in the sense that it uses an algebraic equation to generate the PWM pulses to control the inverter. Experiments, carried out by online microcomputer operation, show that Dual Slope and Dual Slope-variable window width operation result in improved performance.
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Performance analysis of online Dual Slope delta modulated PWM inverter
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: R. Razali, V. Subbiah, M.a. Choudhury, R. YusofAbstract:Delta modulation (DM) is a simple pulse width modulation (PWM) scheme especially suitable for AC machine drives where a constant flux operation is desired. However, the modulator has inferior characteristics when compared to conventional sine PWM and therefore it is not normally used. The disadvantages of delta modulators can be significantly reduced by allowing online parameter variation and synchronous operation. This paper attempts to identify the modulation parameters of a delta modulator, which can be varied during constant and variable frequency operation of the three-phase voltage source inverter (VSI) so as to improve the performance in terms of harmonic content and fundamental voltage availability. A new technique of implementing the delta modulator by a microcomputer is proposed. The method is novel in the sense that it uses an algebraic equation to generate the PWM pulses to control the inverter. Experiments, carried out by online microcomputer operation, show that Dual Slope and Dual Slope-variable window width operation result in improved performance.
Riadh M. Arefin - One of the best experts on this subject based on the ideXlab platform.
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Computationally efficient QRS detection analysis based on Dual-Slope method
2014 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014Co-Authors: Riadh M. Arefin, Reza Fazel-rezaiAbstract:This paper presents a computationally efficient QRS detection algorithm for wearable electrocardiogram (ECG) applications based on Dual-Slope analysis. In general, ECG signals of arrhythmias are pseudo-periodic and contaminated with noises like the patient's contraction muscles, respiration, 60 Hz interference and other types which impede correct QRS detection. To resolve this problem, in this paper, a technique is presented which is based on two Slopes on both sides of a peak in ECG signal. Based on these Slopes, a variable measuring steepness is developed and R peaks are detected. The algorithm was evaluated against MIT/BIH arrhythmia database and achieved 99.38% detection rate. This method was compared with one of the recently developed Dual-Slope based QRS detection methods. The results showed that the proposed method has 12.48 times faster runtime than the old method.
Zhihua Wang - One of the best experts on this subject based on the ideXlab platform.
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A Dual-Slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Shuilong Huang, Zhihua WangAbstract:A Dual-Slope PFD (phase-frequency detector)/CP (charge pump) frequency synthesizer architecture for reducing the settling time of the loop is presented in the paper, which can achieve automatic adjustment of the loop bandwidth and high spectral purity. An adaptive self-tuning algorithm is introduced to effectively enlarge the frequency tuning range in a low VCO gain, where the aim of the adaptive control is for fast convergence to a proper control word. The on-chip VCO achieves a low phase noise by utilizing a tail-current filter technique and a differential inductor, and a 3-4GHz tuning range by a switched capacitor array. Based on 0.18μm 1.8V CMOS technology, simulation shows that the frequency synthesizer has a
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ISCAS - A Dual-Slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithm
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Shuilong Huang, Zhihua WangAbstract:A Dual-Slope PFD (phase-frequency detector)/CP (charge pump) frequency synthesizer architecture for reducing the settling time of the loop is presented in the paper, which can achieve automatic adjustment of the loop bandwidth and high spectral purity. An adaptive self-tuning algorithm is introduced to effectively enlarge the frequency tuning range in a low VCO gain, where the aim of the adaptive control is for fast convergence to a proper control word. The on-chip VCO achieves a low phase noise by utilizing a tail-current filter technique and a differential inductor, and a 3-4GHz tuning range by a switched capacitor array. Based on 0.18mum 1.8V CMOS technology, simulation shows that the frequency synthesizer has a
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a Dual Slope pfd cp frequency synthesizer architecture with an adaptive self tuning algorithm
International Symposium on Circuits and Systems, 2007Co-Authors: Shuilong Huang, Zhihua WangAbstract:A Dual-Slope PFD (phase-frequency detector)/CP (charge pump) frequency synthesizer architecture for reducing the settling time of the loop is presented in the paper, which can achieve automatic adjustment of the loop bandwidth and high spectral purity. An adaptive self-tuning algorithm is introduced to effectively enlarge the frequency tuning range in a low VCO gain, where the aim of the adaptive control is for fast convergence to a proper control word. The on-chip VCO achieves a low phase noise by utilizing a tail-current filter technique and a differential inductor, and a 3-4GHz tuning range by a switched capacitor array. Based on 0.18mum 1.8V CMOS technology, simulation shows that the frequency synthesizer has a <15mus settling time, and the phase noise is lower than -121Bc@ 1MHz.
Richard Gaggl - One of the best experts on this subject based on the ideXlab platform.
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ESSCIRC - A Low-Power Auto-Zero Switched-Capacitor Dual-Slope Noise-Shaping Direct CDC
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018Co-Authors: Christopher Rogi, E. Prefasi, Richard GagglAbstract:A noise-shaping Dual-Slope based complete Switched-Capacitor (SC) direct Capacitance-to-Digital Converter (CDC) for differential sensors has been proven on silicon. The proposed topology does not need a pre-amplifier to interface the sensor. Direct SC sensor readout and single-bit circuitry show to be very area efficient. A SC single-bit capacitive DAC is used during digitization. Auto-zeroing is implemented within the complete SC approach of an inherently robust Dual-Slope converter. Additionally, quantization noise-shaping reduces the measurement time. A prototype is realized in 0.13µm CMOS technology. A 3.2ms measurement results in 13bit resolution while consuming 35µA from a 1.5V supply occupying 0.148mm2.1
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A High-Resolution Self-Oscillating Integrating Dual-Slope CDC for MEMS Sensors
Hybrid ADCs Smart Sensors for the IoT and Sub-1V & Advanced Node Analog Circuit Design, 2018Co-Authors: J. P. Sanjurjo, Enrique Prefasi, C. Rogi, Cesare Buffa, Richard GagglAbstract:An integrating Dual-Slope (DS) capacitance-to-digital converter (CDC), specifically designed for interfacing capacitive MEMS sensors, is presented. In particular, this work proposes a CDC that interfaces a MEMS sensor built with a bridge of capacitors. In this bridge, some capacitances are pressure sensitive, causing pressure-related changes in the bridge output. The voltage to digital conversion is then realized in two steps. First, a voltage amplifier boosts the output of the bridge. Second, an integrating DS ADC digitizes the output of the amplifier. The proposed ADC uses time instead of amplitude resolution to generate a multi-bit digital output stream. In addition, it performs noise shaping of the quantization error to reduce measurement time. These characteristics lead to the following properties: intrinsically low sensitivity to temperature and process variations, simplicity of trimming offset and gain to correct for sensor parameter spread, and an energy-efficient implementation. The effectiveness of the proposed architecture is demonstrated by measurements performed on a prototype, designed, and fabricated using standard 0.13 μm CMOS technology. Experimental results show that the proposed CDC achieves a maximum resolution of 17 bits, which corresponds to a capacitive resolution of 5.4aF, while consuming only 146 μA from a 1.5 V power supply, with an effective area of 0.317mm2.
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A Low-Power Auto-Zero Switched-Capacitor Dual-Slope Noise-Shaping Direct CDC
ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), 2018Co-Authors: Christopher Rogi, Enrique Prefasi, Richard GagglAbstract:A noise-shaping Dual-Slope based complete Switched-Capacitor (SC) direct Capacitance-to-Digital Converter (CDC) for differential sensors has been proven on silicon. The proposed topology does not need a pre-amplifier to interface the sensor. Direct SC sensor readout and single-bit circuitry show to be very area efficient. A SC single-bit capacitive DAC is used during digitization. Auto-zeroing is implemented within the complete SC approach of an inherently robust Dual-Slope converter. Additionally, quantization noise-shaping reduces the measurement time. A prototype is realized in 0.13μm CMOS technology. A 3.2ms measurement results in 13bit resolution while consuming 35μA from a 1.5V supply occupying 0.148mm2.1.
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ESSCIRC - An energy-efficient 17-bit noise-shaping Dual-Slope Capacitance-to-Digital Converter for MEMS sensors
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016Co-Authors: J. P. Sanjurjo, Cesare Buffa, E. Prefasi, Richard GagglAbstract:A noise-shaping Dual-Slope (DS) Capacitance-to-Digital Converter (CDC), specifically designed for interfacing capacitive MEMS sensors, is presented. In particular, this work proposes a design with a MEMS sensor built with a bridge of capacitors. In this bridge, some capacitors are function of the pressure in order to obtain a variation in the output of the bridge related with the change of pressure. Then, the capacitive to digital conversion is realized using two steps. First, a Switched-Capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a time domain noise-shaping Dual-Slope ADC is used to digitalize the magnitude of the capacitive bridge. The use of time instead of amplitude resolution leads to the following strengths: 1) intrinsically small sensitivity to temperature and process variations; 2) simplicity of trimming offset and gain to correct the sensor parameter spread; and 3) area and energy efficient implementation. The effectiveness of the method is demonstrated by measurements performed on a prototype, designed and fabricated using standard digital 0.13µm CMOS technology. Experimental results show that it achieves a resolution of 17-bit, which corresponds to a capacitive resolution of 5.4aF, while consuming only 146µA from a 1.5V power supply, with an effective area of 0.317mm2.
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An energy-efficient 17-bit noise-shaping Dual-Slope Capacitance-to-Digital Converter for MEMS sensors
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016Co-Authors: J. P. Sanjurjo, Cesare Buffa, E. Prefasi, Richard GagglAbstract:A noise-shaping Dual-Slope (DS) Capacitance-to-Digital Converter (CDC), specifically designed for interfacing capacitive MEMS sensors, is presented. In particular, this work proposes a design with a MEMS sensor built with a bridge of capacitors. In this bridge, some capacitors are function of the pressure in order to obtain a variation in the output of the bridge related with the change of pressure. Then, the capacitive to digital conversion is realized using two steps. First, a Switched-Capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a time domain noise-shaping Dual-Slope ADC is used to digitalize the magnitude of the capacitive bridge. The use of time instead of amplitude resolution leads to the following strengths: 1) intrinsically small sensitivity to temperature and process variations; 2) simplicity of trimming offset and gain to correct the sensor parameter spread; and 3) area and energy efficient implementation. The effectiveness of the method is demonstrated by measurements performed on a prototype, designed and fabricated using standard digital 0.13μm CMOS technology. Experimental results show that it achieves a resolution of 17-bit, which corresponds to a capacitive resolution of 5.4aF, while consuming only 146μA from a 1.5V power supply, with an effective area of 0.317mm2.
