The Experts below are selected from a list of 8607 Experts worldwide ranked by ideXlab platform
Ettore Napoli - One of the best experts on this subject based on the ideXlab platform.
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FPGA-based architecture for real time segmentation and denoising of HD video
Journal of Real-Time Image Processing, 2013Co-Authors: Marco Genovese, Ettore NapoliAbstract:The identification of moving objects is a basic step in computer vision. The identification begins with the segmentation and is followed by a denoising phase. This paper proposes the FPGA hardware implementation of segmentation and denoising unit. The segmentation is conducted using the Gaussian mixture model (GMM), a probabilistic method for the segmentation of the background. The denoising is conducted implementing the morphological operators of erosion, dilation, opening and closing. The proposed circuit is optimized to perform real time processing of HD video sequences (1,920 × 1,080 @ 20 fps) when implemented on FPGA devices. The circuit uses an optimized fixed width representation of the data and implements high performance arithmetic circuits. The circuit is implemented on Xilinx and Altera FPGA. Implemented on xc5vlx50 Virtex5 FPGA, it can process 24 fps of an HD video using 1,179 Slice LUTs and 291 Slice Registers; the Dynamic Power Dissipation is 0.46 mW/MHz. Implemented on EP2S15F484C3 StratixII, it provides a maximum working frequency of 44.03 MHz employing 5038 Logic Elements and 7,957 flip flop with a Dynamic Power Dissipation of 4.03 mW/MHz.
Marco Genovese - One of the best experts on this subject based on the ideXlab platform.
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FPGA-based architecture for real time segmentation and denoising of HD video
Journal of Real-Time Image Processing, 2013Co-Authors: Marco Genovese, Ettore NapoliAbstract:The identification of moving objects is a basic step in computer vision. The identification begins with the segmentation and is followed by a denoising phase. This paper proposes the FPGA hardware implementation of segmentation and denoising unit. The segmentation is conducted using the Gaussian mixture model (GMM), a probabilistic method for the segmentation of the background. The denoising is conducted implementing the morphological operators of erosion, dilation, opening and closing. The proposed circuit is optimized to perform real time processing of HD video sequences (1,920 × 1,080 @ 20 fps) when implemented on FPGA devices. The circuit uses an optimized fixed width representation of the data and implements high performance arithmetic circuits. The circuit is implemented on Xilinx and Altera FPGA. Implemented on xc5vlx50 Virtex5 FPGA, it can process 24 fps of an HD video using 1,179 Slice LUTs and 291 Slice Registers; the Dynamic Power Dissipation is 0.46 mW/MHz. Implemented on EP2S15F484C3 StratixII, it provides a maximum working frequency of 44.03 MHz employing 5038 Logic Elements and 7,957 flip flop with a Dynamic Power Dissipation of 4.03 mW/MHz.
James D. Meindl - One of the best experts on this subject based on the ideXlab platform.
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a stochastic wire length distribution for gigascale integration gsi ii applications to clock frequency Power Dissipation and chip size estimation
IEEE Transactions on Electron Devices, 1998Co-Authors: Jeffrey A. Davis, Vivek De, James D. MeindlAbstract:For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary Dynamic Power Dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size.
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A stochastic wire length distribution for gigascale integration (GSI)
Proceedings of CICC 97 - Custom Integrated Circuits Conference, 1Co-Authors: Jeffrey A. Davis, James D. MeindlAbstract:Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. This distribution is used to enhance a critical path model; to derive a preliminary Dynamic Power Dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density.
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Optimal low Power interconnect networks
1996 Symposium on VLSI Technology. Digest of Technical Papers, 1Co-Authors: Jeffrey A. Davis, James D. MeindlAbstract:Because interconnect capacitance represents the dominant load capacitance in CMOS VLSI systems, Dynamic Power Dissipation is largely determined by multilevel wiring requirements. Using a newly derived stochastic interconnect distribution, a model for total on-chip Power Dissipation is developed. With this new model, the optimal interconnect dimensions for a multilevel network can be determined that minimize chip size and Power drain.
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An upper limit for aggregate I/O interconnect bandwidth of GSI chips constrained by Power Dissipation
Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729), 1Co-Authors: Aa. Naeemi, James D. MeindlAbstract:For the first time, the average energy Dissipation per input/output bits is estimated, which is very useful in determining an upper bound for chip aggregate I/O bandwidth for a given Dynamic Power budget. Some empirical parameters such as Rent's parameters and activity factor are used to capture the impact of chip architecture. For a projected multiprocessor implemented at the 45 nm technology node it is shown that 30 Tb/s is the maximum aggregate I/O bandwidth for 100W Dynamic Power Dissipation.
Jeffrey A. Davis - One of the best experts on this subject based on the ideXlab platform.
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a stochastic wire length distribution for gigascale integration gsi ii applications to clock frequency Power Dissipation and chip size estimation
IEEE Transactions on Electron Devices, 1998Co-Authors: Jeffrey A. Davis, Vivek De, James D. MeindlAbstract:For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary Dynamic Power Dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size.
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A stochastic wire length distribution for gigascale integration (GSI)
Proceedings of CICC 97 - Custom Integrated Circuits Conference, 1Co-Authors: Jeffrey A. Davis, James D. MeindlAbstract:Based on Rent's Rule, a well established empirical relationship, a rigorous derivation of a complete wire length distribution for on-chip random logic networks is performed. This distribution is used to enhance a critical path model; to derive a preliminary Dynamic Power Dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density.
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Optimal low Power interconnect networks
1996 Symposium on VLSI Technology. Digest of Technical Papers, 1Co-Authors: Jeffrey A. Davis, James D. MeindlAbstract:Because interconnect capacitance represents the dominant load capacitance in CMOS VLSI systems, Dynamic Power Dissipation is largely determined by multilevel wiring requirements. Using a newly derived stochastic interconnect distribution, a model for total on-chip Power Dissipation is developed. With this new model, the optimal interconnect dimensions for a multilevel network can be determined that minimize chip size and Power drain.
Noureddine Chabini - One of the best experts on this subject based on the ideXlab platform.
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Level-converter aware supply voltage scaling for reducing Dynamic Power Dissipation in clocked sequential designs
2009 International Conference on Multimedia Computing and Systems, 2009Co-Authors: Noureddine ChabiniAbstract:In this paper, we propose a Mixed Integer Linear Program (MILP) to solve the problem of optimal unification of low-supply-voltage assignment and retiming to reduce Dynamic Power Dissipation under timing constrains for the case of clocked sequential digital designs. We address this problem at the system level where computational elements are multipliers and adders for instance. Assuming flip-flops are able to provide level-conversion from low to high supply voltage when this is needed, the proposed MILP optimally solves this problem without inserting level converters on wires that do not have registers on them. Experimental results have shown that this MILP can produce designs with reduced Dynamic Power Dissipation.
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a heuristic for reducing Dynamic Power Dissipation in clocked sequential designs
Power and Timing Modeling Optimization and Simulation, 2007Co-Authors: Noureddine ChabiniAbstract:Assigning computational elements to low supply voltages can reduce Dynamic Power Dissipation, but increase execution delays. The problem of reducing Dynamic Power consumption by assigning low supply voltages to computational elements off critical paths is NP-hard in general. It has been addressed in the case of combinational designs. It becomes more difficult in the case of clocked sequential designs since critical paths are defined relative to the position of registers. By repositioning some registers, some computational elements could be moved from critical paths, and hence their supply voltages can be scaled down. In this paper, we propose a polynomial time algorithm to determine solutions to this problem in the case of clocked sequential designs. Experimental results have shown that the proposed algorithm is able to significantly reduce Dynamic Power Dissipation.
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PATMOS - A Heuristic for reducing Dynamic Power Dissipation in clocked sequential designs
Lecture Notes in Computer Science, 1Co-Authors: Noureddine ChabiniAbstract:Assigning computational elements to low supply voltages can reduce Dynamic Power Dissipation, but increase execution delays. The problem of reducing Dynamic Power consumption by assigning low supply voltages to computational elements off critical paths is NP-hard in general. It has been addressed in the case of combinational designs. It becomes more difficult in the case of clocked sequential designs since critical paths are defined relative to the position of registers. By repositioning some registers, some computational elements could be moved from critical paths, and hence their supply voltages can be scaled down. In this paper, we propose a polynomial time algorithm to determine solutions to this problem in the case of clocked sequential designs. Experimental results have shown that the proposed algorithm is able to significantly reduce Dynamic Power Dissipation.
