The Experts below are selected from a list of 63405 Experts worldwide ranked by ideXlab platform
A.a. Jerraya - One of the best experts on this subject based on the ideXlab platform.
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fast and accurate timed execution of high level embedded software using hw sw interface simulation model
Asia and South Pacific Design Automation Conference, 2004Co-Authors: A. Bouchhima, A.a. JerrayaAbstract:In this paper, we propose a methodology to perform Early Design Stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS abstraction level and a HW Platform described at an arbitrary abstraction level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an Early Design Stage before the system Design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).
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Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model
2004Co-Authors: A. Bouchhima, S. Yoo, A.a. JerrayaAbstract:We propose a methodology to perform Early Design Stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS abstraction level and a HW platform described at an arbitrary abstraction level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an Early Design Stage before the system Design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).
Lieven Eeckhout - One of the best experts on this subject based on the ideXlab platform.
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power aware multi core simulation for Early Design Stage hardware software co optimization
International Conference on Parallel Architectures and Compilation Techniques, 2012Co-Authors: Wim Heirman, Souradip Sarkar, Trevor E Carlson, Ibrahim Hur, Lieven EeckhoutAbstract:Stringent performance targets and power constraints push Designers towards building specialized workload-optimized systems across a broad spectrum of the computing arena, including supercomputing applications as exemplified by the IBM BlueGene and Intel MIC architectures. In this paper, we make the case for hardware/software co-Design during Early Design Stages of processors for scientific computing applications. Considering an important scientific kernel, namely stencil computation, we demonstrate that performance and energy-efficiency can be improved by a factor of 1.66× and 1.25×, respectively, by co-optimizing hardware and software. To enable hardware/software co-Design in Early Stages of the Design cycle, we propose a novel simulation infrastructure by combining high-abstraction performance simulation using Sniper with power modeling using McPAT and custom DRAM power models. Sniper/McPAT is fast — simulation speed is around 2 MIPS on an 8-core host machine — because it uses analytical modeling to abstract away core performance during multi-core simulation. We demonstrate Sniper/McPAT's accuracy through validation against real hardware; we report average performance and power prediction errors of 22.1% and 8.3%, respectively, for a set of SPEComp benchmarks.
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How accurate should Early Design Stage power/performance tools be? A case study with statistical simulation
Journal of Systems and Software, 2004Co-Authors: Lieven Eeckhout, Koen De BosschereAbstract:To cope with the widening Design gap, the ever increasing impact of technology, reflected in increased interconnect delay and power consumption, and the time-consuming simulations needed to define the architecture of a microprocessor, computer engineers need techniques to explore the Design space efficiently in an Early Design Stage. These techniques should be able to identify a region of interest with desirable characteristics in terms of performance, power consumption and cycle time. In addition, they should be fast since the Design space is huge and the Design time is limited. In this paper, we study how accurate Early Design Stage techniques should be to make correct Design decisions. In this analysis we focus on relative accuracy which is more important than absolute accuracy at the earliest Stages of the Design flow. As a case study we demonstrate that statistical simulation is capable of making viable microprocessor Design decisions efficiently in Early Stages of a microprocessor Design while considering performance, power consumpaion and cycle time.
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Early Design Stage exploration of fixed-length block structured architectures
Journal of Systems Architecture, 2000Co-Authors: Lieven Eeckhout, Henk Neefs, Koen De BosschereAbstract:An important challenge concerning the Design of future microprocessors is that current Design methodologies are becoming impractical due to long simulation runs and due to the fact that chip layout considerations are not incorporated in Early Design Stages. In this paper, we show that statistical modeling can be used to speed up the architectural simulations and is thus viable for Early Design Stage explorations of new microarchitectures. In addition, we argue that processor layouts should be considered in Early Design Stages in order to tackle the growing importance of interconnects in future technologies. In order to show the applicability of our methodology which combines statistical modeling and processor layout considerations in an Early Design Stage, we have applied our method on a novel architectural paradigm, namely a fixed-length block structured architecture. A fixed-length block structured architecture is an answer to the scalability problem of current architectures. Two important factors prevent contemporary out-of-order architectures from being scalable to higher levels of parallelism in future deep-submicron technologies: the increased complexity and the growing domination of interconnect delays. In this paper, we show by using statistical modeling and processor layout considerations, that a fixed-length block structured architecture is a viable architectural paradigm for future microprocessors in future technologies thanks to the introduction of decentralization and a reduced register file pressure.
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EUROMICRO - Investigating the implementation of a block structured processor architecture in an Early Design Stage
Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium, 1999Co-Authors: Lieven Eeckhout, Henk Neefs, K. De Bosschere, J. Van CampenhoutAbstract:When Designing a new micro-architecture, it is difficult to estimate the influence of the architectural parameters on clock period and chip area. In this paper, we use automatic synthesis to investigate the implementation of a novel processor architecture, namely a block structured instruction set architecture (BSA). In a BSA, instructions are statically grouped into fixed-length blocks by the compiler and the execution policy within a block is data-flow. The use of automatic synthesis is forced by the fact that a broad Design space is investigated in an Early Design Stage. The three parameters that we specifically focus on are blocksize, instruction selection window size and issue width. Various pipeline configurations are investigated. Moreover, we investigate the effect of technology scaling on the selection of the best architecture and pipeline configuration; we consider both a 0.8 /spl mu/m 2-metal layer CMOS technology and a more advanced 0.25 /spl mu/m 6-metal layer CMOS technology. From this paper we can conclude that a BSA has several implementational benefits over traditional architectures due to the partitioned Design and the reduced wiring delays.
Philipp Geyer - One of the best experts on this subject based on the ideXlab platform.
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Quick energy prediction and comparison of options at the Early Design Stage
Advanced Engineering Informatics, 2020Co-Authors: Manav Mahan Singh, Sundaravelpandian Singaravel, Ralf Klein, Philipp GeyerAbstract:Abstract The energy-efficient building Design requires building performance simulation (BPS) to compare multiple Design options for their energy performance. However, at the Early Stage, BPS is often ignored, due to uncertainty, lack of details, and computational time. This article studies probabilistic and deterministic approaches to treat uncertainty; detailed and simplified zoning for creating zones; and dynamic simulation and machine learning for making energy predictions. A state-of-the-art approach, such as dynamic simulation, provide a reliable estimate of energy demand, but computationally expensive. Reducing computational time requires the use of an alternative approach, such as a machine learning (ML) model. However, an alternative approach will cause a prediction gap, and its effect on comparing options needs to be investigated. A plugin for Building information modelling (BIM) modelling tool has been developed to perform BPS using various approaches. These approaches have been tested for an office building with five Design options. A method using the probabilistic approach to treat uncertainty, detailed zoning to create zones, and EnergyPlus to predict energy is treated as the reference method. The deterministic or ML approach has a small prediction gap, and the comparison results are similar to the reference method. The simplified model approach has a large prediction gap and only makes only 40% comparison results are similar to the reference method. These findings are useful to develop a BIM integrated tool to compare options at the Early Design Stage and ascertain which approach should be adopted in a time-constraint situation.
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deep convolutional learning for general Early Design Stage prediction models
Advanced Engineering Informatics, 2019Co-Authors: Sundaravelpandian Singaravel, Johan A K Suykens, Philipp GeyerAbstract:Abstract Designers rely on performance predictions to direct the Design toward appropriate requirements. Machine learning (ML) models exhibit the potential for rapid and accurate predictions. Developing conventional ML models that can be generalized well in unseen Design cases requires an effective feature engineering and selection. Identifying generalizable features calls for good domain knowledge by the ML model developer. Therefore, developing ML models for all Design performance parameters with conventional ML will be a time-consuming and expensive process. Automation in terms of feature engineering and selection will accelerate the use of ML models in Design. Deep learning models extract features from data, which aid in model generalization. In this study, we (1) evaluate the deep learning model’s capability to predict the heating and cooling demand on unseen Design cases and (2) obtain an understanding of extracted features. Results indicate that deep learning model generalization is similar to or better than that of a simple neural network with appropriate features. The reason for the satisfactory generalization using the deep learning model is its ability to identify similar Design options within the data distribution. The results also indicate that deep learning models can filter out irrelevant features, reducing the need for feature selection.
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Deep Component-Based Neural Network Energy Modelling for Early Design Stage Prediction
Design Computing and Cognition '18, 2019Co-Authors: Sundaravelpandian Singaravel, Philipp GeyerAbstract:Developing low-energy buildings calls for low-energy Design and operations. Estimating operational energy of a building Design supports major decisions taken at Early Design Stages. To support Early Design decisions, accurate and quick predictions are required; a decision taken on predictions with poor quality can result in a wrong decision.
A. Bouchhima - One of the best experts on this subject based on the ideXlab platform.
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fast and accurate timed execution of high level embedded software using hw sw interface simulation model
Asia and South Pacific Design Automation Conference, 2004Co-Authors: A. Bouchhima, A.a. JerrayaAbstract:In this paper, we propose a methodology to perform Early Design Stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS abstraction level and a HW Platform described at an arbitrary abstraction level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an Early Design Stage before the system Design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).
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Fast and accurate timed execution of high level embedded software using HW/SW interface simulation model
2004Co-Authors: A. Bouchhima, S. Yoo, A.a. JerrayaAbstract:We propose a methodology to perform Early Design Stage validation of hardware/software (HW/SW) systems using a HW/SW interface simulation model. Given a SW application described at the OS abstraction level and a HW platform described at an arbitrary abstraction level, we aim at providing the adaptation layer, i.e. simulation model of the HW/SW interface, which will enable the timed HW/SW cosimulation of the entire system at an Early Design Stage before the system Design is completed. Experimental results show that our approach is easy to use and efficient while providing fast simulation (up to 3 orders of magnitude faster than a HW/SW cosimulation with instruction set simulator, ISS) and accuracy (86% compared with a HW/SW cosimulation with ISS).
Stefan Kruger - One of the best experts on this subject based on the ideXlab platform.
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computation of drift forces for dynamic positioning within the very Early Design Stage of offshore wind farm installation vessels
ASME 2014 33rd International Conference on Ocean Offshore and Arctic Engineering, 2014Co-Authors: Philip H Augener, Stefan KrugerAbstract:The German government has decided upon the changeover from fossil and nuclear based electrical power generation to renewable energies. Following from this offshore wind farms are erected in the exclusive economic zones of Germany. For the transportation and installation as well as the maintenance of the wind turbine generators very specialized vessels are needed. The capability of dynamic positioning even in very harsh weather conditions is one of the major Design tasks for these vessels. For this reason it is important to know the external loads on the ships during station keeping already in the very Early Design Stage. This paper focuses on the computation of wave drift forces in regular and irregular waves as well as in natural seaway. For validation the results of the introduced calculation procedure are compared to measured drift force data from sea-keeping tests of an Offshore Wind Farm Transport and Installation Vessel.© 2014 ASME
