The Experts below are selected from a list of 237 Experts worldwide ranked by ideXlab platform
Mithuna Thottethodi - One of the best experts on this subject based on the ideXlab platform.
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ISLPED - PreTrans: reducing TLB CAM-search via page number prediction and speculative pre-translation
International Symposium on Low Power Electronics and Design (ISLPED), 2013Co-Authors: Mithuna ThottethodiAbstract:The need for fast Address translation within tight time constraints (before L1 tag check but after Effective Address computation) imposes many design constraints. The freedom from such constraints can potentially lead to lower TLB energy costs. In this paper, we observe that (1) data accesses commonly use base-displacement Addressing modes in which the Effective Address is computed as the sum of a base and a displacement, and (2) the Effective page numbers are predictable once the base Address is known. Further, it is easy to cache Address translations alongside the predicted page numbers thus enabling speculative Address translation that can filter accesses to the TLB. The two observations enable our PreTrans design in which (a) a speculative translation is available based solely on the base Address, and (b) the translation is available simultaneously with the Effective (virtual) Address. PreTrans replaces most of the energy-expensive CAM-lookups for TLB access with RAM lookups, which translates to significant power improvements in the TLB.
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PreTrans: Reducing TLB CAM-search via page number prediction and speculative pre-translation
International Symposium on Low Power Electronics and Design (ISLPED), 2013Co-Authors: Mithuna ThottethodiAbstract:The need for fast Address translation within tight time constraints (before L1 tag check but after Effective Address computation) imposes many design constraints. The freedom from such constraints can potentially lead to lower TLB energy costs. In this paper, we observe that (1) data accesses commonly use base-displacement Addressing modes in which the Effective Address is computed as the sum of a base and a displacement, and (2) the Effective page numbers are predictable once the base Address is known. Further, it is easy to cache Address translations alongside the predicted page numbers thus enabling speculative Address translation that can filter accesses to the TLB. The two observations enable our PreTrans design in which (a) a speculative translation is available based solely on the base Address, and (b) the translation is available simultaneously with the Effective (virtual) Address. PreTrans replaces most of the energy-expensive CAM-lookups for TLB access with RAM lookups, which translates to significant power improvements in the TLB.
Gurindar S. Sohi - One of the best experts on this subject based on the ideXlab platform.
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ISCA - Streamlining data cache access with fast Address calculation
Proceedings of the 22nd annual international symposium on Computer architecture - ISCA '95, 1995Co-Authors: Todd Austin, Dionisios Pnevmatikatos, Gurindar S. SohiAbstract:For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the design and evaluation of a fast Address generation mechanism capable of eliminating the delays caused by Effective Address calculation for many loads and stores.Our approach works by predicting early in the pipeline (part of) the Effective Address of a memory access and using this predicted Address to speculatively access the data cache. If the prediction is correct, the cache access is overlapped with non-speculative Effective Address calculation. Otherwise, the cache is accessed again in the following cycle, this time using the correct Effective Address. The impact on the cache access critical path is minimal; the prediction circuitry adds only a single OR operation before cache access can commence. In addition, verification of the predicted Effective Address is completely decoupled from the cache access critical path.Analyses of program reference behavior and subsequent performance analysis of this approach shows that this design is a good one, servicing enough accesses early enough to result in speedups for all the programs we tested. Our approach also responds well to software support, which can significantly reduce the number of mispredicted Effective Addresses, in many cases providing better program speedups and reducing cache bandwidth requirements.
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Streamlining data cache access with fast Address calculation
Proceedings 22nd Annual International Symposium on Computer Architecture, 1995Co-Authors: T.m. Austin, Dionisios Pnevmatikatos, Gurindar S. SohiAbstract:For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the design and evaluation of a fast Address generation mechanism capable of eliminating the delays caused by Effective Address calculation for many loads and stores. Our approach works by predicting early in the pipeline (part of) the Effective Address of a memory access and using this predicted Address to speculatively access the data cache. If the prediction is correct, the cache access is overlapped with non-speculative Effective Address calculation. Otherwise, the cache is accessed again in the following cycle, this time using the correct Effective Address. The impact on the cache access critical path is minimal; the prediction circuitry adds only a single OR operation before cache access can commence. In addition, verification of the predicted Effective Address is completely decoupled from the cache access critical path. Analyses of program reference behavior and subsequent performance analysis of this approach shows that this design is a good one, servicing enough accesses early enough to result in speedups for all the programs we tested. Our approach also responds well to software support, which can significantly reduce the number of mispredicted Effective Addresses, in many cases providing better program speedups and reducing cache bandwidth requirements.
A. Olive - One of the best experts on this subject based on the ideXlab platform.
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IEEE PACT - Split last-Address predictor
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: E. Morancho, J.m. Llaberia, A. OliveAbstract:Recent works have proposed the use of prediction techniques to execute speculatively true data-dependent operations. However, the predictability of the operations do not spread uniformly among them. Then, we propose the use of run-time classification of instructions to increase the efficiency of the predictors. At run time, the proposed mechanism classifies instructions according to their predictability, decoupling this classification from prediction table. Then, the classification is used to avoid the unpredictable instructions from being candidates to allocate an entry in the prediction table. The previous idea of run-time classification is applied to the last-Address predictor (Split Last-Address Predictor). The goal of this predictor is to reduce the latency of load instructions. Memory access is performed after the Effective Address is predicted concurrently with instruction fetch, after that, next true data-dependent instructions can be executed speculatively. We show that our proposal applied to the last-Address predictor captures the same predictability than the last-Address predictor proposed in literature, increases its accuracy, and reduces its area-cost by 19%.
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Split last-Address predictor
Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192), 1998Co-Authors: E. Morancho, J.m. Llaberia, A. OliveAbstract:Recent works have proposed the use of prediction techniques to execute speculatively true data-dependent operations. However, the predictability of the operations do not spread uniformly among them. Then, we propose the use of run-time classification of instructions to increase the efficiency of the predictors. At run time, the proposed mechanism classifies instructions according to their predictability, decoupling this classification from prediction table. Then, the classification is used to avoid the unpredictable instructions from being candidates to allocate an entry in the prediction table. The previous idea of run-time classification is applied to the last-Address predictor (Split Last-Address Predictor). The goal of this predictor is to reduce the latency of load instructions. Memory access is performed after the Effective Address is predicted concurrently with instruction fetch, after that, next true data-dependent instructions can be executed speculatively. We show that our proposal applied to the last-Address predictor captures the same predictability than the last-Address predictor proposed in literature, increases its accuracy, and reduces its area-cost by 19%.
T.m. Austin - One of the best experts on this subject based on the ideXlab platform.
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Improving the accuracy and performance of memory communication through renaming
Proceedings of 30th Annual International Symposium on Microarchitecture, 1997Co-Authors: G.s. Tyson, T.m. AustinAbstract:As processors continue to exploit more instruction-level parallelism, a greater demand is placed on reducing the effects of memory access latency. In this paper, we introduce a novel modification of the processor pipeline called memory renaming. Memory renaming applies register access techniques to load instructions, reducing the effect of delays caused by the need to calculate Effective Addresses for the load and all preceding stores before the data can be fetched. Memory renaming allows the processor to speculatively fetch values when the producer of the data can be reliably determined without the need for an Effective Address. This work extends previous studies of data value and dependence speculation. When memory renaming is added to the processor pipeline, renaming can be applied to 30% to 50% of all memory references, translating to an overall improvement in execution time of up to 41%. Furthermore, this improvement is seen across all memory segments-including the heap segment, which has often been difficult to manage efficiently.
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Streamlining data cache access with fast Address calculation
Proceedings 22nd Annual International Symposium on Computer Architecture, 1995Co-Authors: T.m. Austin, Dionisios Pnevmatikatos, Gurindar S. SohiAbstract:For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the design and evaluation of a fast Address generation mechanism capable of eliminating the delays caused by Effective Address calculation for many loads and stores. Our approach works by predicting early in the pipeline (part of) the Effective Address of a memory access and using this predicted Address to speculatively access the data cache. If the prediction is correct, the cache access is overlapped with non-speculative Effective Address calculation. Otherwise, the cache is accessed again in the following cycle, this time using the correct Effective Address. The impact on the cache access critical path is minimal; the prediction circuitry adds only a single OR operation before cache access can commence. In addition, verification of the predicted Effective Address is completely decoupled from the cache access critical path. Analyses of program reference behavior and subsequent performance analysis of this approach shows that this design is a good one, servicing enough accesses early enough to result in speedups for all the programs we tested. Our approach also responds well to software support, which can significantly reduce the number of mispredicted Effective Addresses, in many cases providing better program speedups and reducing cache bandwidth requirements.
Yale N. Patt - One of the best experts on this subject based on the ideXlab platform.
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Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses
IEEE Transactions on Computers, 2006Co-Authors: Onur Mutlu, Yale N. PattAbstract:While runahead execution is Effective at parallelizing independent long-latency cache misses, it is unable to parallelize dependent long-latency cache misses. To overcome this limitation, this paper proposes a novel hardware technique, Address-value delta (AVD) prediction. An AVD predictor keeps track of the Address (pointer) load instructions for which the arithmetic difference (i.e., delta) between the Effective Address and the data value is stable. If such a load instruction incurs a long-latency cache miss during runahead execution, its data value is predicted by subtracting the stable delta from its Effective Address. This prediction enables the preexecution of dependent instructions, including load instructions that incur long-latency cache misses. We analyze why and for what kind of loads AVD prediction works and describe the design of an implementable AVD predictor. We also describe simple hardware and software optimizations that can significantly improve the benefits of AVD prediction and analyze the interaction of AVD prediction with runahead efficiency techniques and stream-based data prefetching. Our analysis shows that AVD prediction is complementary to these techniques. Our results show that augmenting a runahead processor with a simple, 16-entry AVD predictor improves the average execution time of a set of pointer-intensive applications by 14.3 percent (7.5 percent excluding benchmark health)
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MICRO - Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns
38th Annual IEEE ACM International Symposium on Microarchitecture (MICRO'05), 2005Co-Authors: Onur Mutlu, Yale N. PattAbstract:While runahead execution is Effective at parallelizing independent long-latency cache misses, it is unable to parallelize dependent long-latency cache misses. To overcome this limitation, this paper proposes a novel technique, Address-value delta (AVD) prediction. An AVD predictor keeps track of the Address (pointer) load instructions for which the arithmetic difference (i.e., delta) between the Effective Address and the data value is stable. If such a load instruction incurs a long-latency cache miss during runahead execution, its data value is predicted by subtracting the stable delta from its Effective Address. This prediction enables the pre-execution of dependent instructions, including load instructions that incur long-latency cache misses. We describe how, why, and for what kind of loads AVD prediction works and evaluate the design tradeoffs in an implementable AVD predictor. Our analysis shows that stable AVDs exist because of patterns in the way data structures are allocated in memory. Our results show that augmenting a runahead processor with a simple, 16-entry AVD predictor improves the average execution time of a set of pointer-intensive applications by 12.1%.
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Address-value delta (AVD) prediction: Increasing the Effectiveness of runahead execution by exploiting regular memory allocation patterns
Proceedings of the Annual International Symposium on Microarchitecture MICRO, 2005Co-Authors: Onur Mutlu, Hyesoon Kim, Yale N. PattAbstract:While runahead execution is Effective at parallelizing independent long-latency cache misses, it is unable to parallelize dependent long-latency cache misses. To overcome this limitation, this paper proposes a novel technique, Address-value delta (AVD) prediction. An AVD predictor keeps track of the Address (pointer) load instructions for which the arithmetic difference (i.e., delta) between the Effective Address and the data value is stable. If such a load instruction incurs a long-latency cache miss during runahead execution, its data value is predicted by subtracting the stable delta from its Effective Address. This prediction enables the pre-execution of dependent instructions, including load instructions that incur long-latency cache misses. We describe how, why, and for what kind of loads AVD prediction works and evaluate the design tradeoffs in an implementable AVD predictor. Our analysis shows that stable AVDs exist because of patterns in the way data structures are allocated in memory. Our results show that augmenting a runahead processor with a simple, 16-entry AVD predictor improves the average execution time of a set of pointer-intensive applications by 12.1%.