The Experts below are selected from a list of 64890 Experts worldwide ranked by ideXlab platform
Frederic T. Chong - One of the best experts on this subject based on the ideXlab platform.
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Synchroscalar: Initial lessons in power-aware design of a tile-based Embedded Architecture
Lecture Notes in Computer Science, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.
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PACS - Synchroscalar: initial lessons in power-aware design of a tile-based Embedded Architecture
Power-Aware Computer Systems, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.
John W. K. Oliver - One of the best experts on this subject based on the ideXlab platform.
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Synchroscalar: Initial lessons in power-aware design of a tile-based Embedded Architecture
Lecture Notes in Computer Science, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.
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PACS - Synchroscalar: initial lessons in power-aware design of a tile-based Embedded Architecture
Power-Aware Computer Systems, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.
A. Crespo - One of the best experts on this subject based on the ideXlab platform.
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Partitioned Embedded Architecture Based on Hypervisor: The XtratuM Approach
2010 European Dependable Computing Conference, 2010Co-Authors: A. Crespo, I. Ripoll, M. MasmanoAbstract:Partitioned software Architectures were conceived to fulfill security and avionics requirements where predictability is extremely important. Both, the availability of new processors and an increased necessity of security, have opened new possibilities to use efficiently this approach. Avionic industry has consolidated the Integrated Modular Avionics (IMA) as a solution to manage the software growth in functionality and in efficiency. Now, the aerospace sector is adapting these concepts on its developments. One of the solutions used to achieve partitioned systems is based on virtualisation techniques. In this paper we present XtratuM, a bare-metal hypervisor which implements para-virtualization and dedicated device techniques. XtratuM provides a virtual machine that is 'near' the native one. It permits to execute a set of partitions, containing each one an operating systems and its applications. Security is based on the temporal and spatial isolation properties provided by the hypervisor. This paper describes the main design criteria used to achieve temporal and spatial partition isolation and an approach to extend the trusted environment from the hardware level to the hypervisor level in order to verify the temporal and spatial isolation properties
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EDCC - Partitioned Embedded Architecture Based on Hypervisor: The XtratuM Approach
2010 European Dependable Computing Conference, 2010Co-Authors: A. Crespo, I. Ripoll, M. MasmanoAbstract:Partitioned software Architectures were conceived to fulfill security and avionics requirements where predictability is extremely important. Both, the availability of new processors and an increased necessity of security, have opened new possibilities to use efficiently this approach. Avionic industry has consolidated the Integrated Modular Avionics (IMA) as a solution to manage the software growth in functionality and in efficiency. Now, the aerospace sector is adapting these concepts on its developments. One of the solutions used to achieve partitioned systems is based on virtualisation techniques. In this paper we present XtratuM, a bare-metal hypervisor which implements para-virtualization and dedicated device techniques. XtratuM provides a virtual machine that is 'near' the native one. It permits to execute a set of partitions, containing each one an operating systems and its applications. Security is based on the temporal and spatial isolation properties provided by the hypervisor. This paper describes the main design criteria used to achieve temporal and spatial partition isolation and an approach to extend the trusted environment from the hardware level to the hypervisor level in order to verify the temporal and spatial isolation properties
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Real-time Embedded Architecture for improving Pervasive Robot Services
2008Co-Authors: C. Dominguez, Houcine Hassan, A. CrespoAbstract:The integration of Embedded real-time control systems with the physical world via sensors and actuators (pervasive computing systems) is creating a nascent infrastructure for a technical, economic and social revolution. Service robots have to execute tasks that have different criticality, flexible timing constraints and variable execution time, because they perform their activities in dynamic and unpredictable environments, they share resources and have to cooperate to fulfill the objectives. The environmental conditions have influence in the variability of the system load. For instance, the computational requirements of recognition tasks are variable and dependent on the number of objects perceived in scenes. To tackle the computational variability of pervasive robots a real-time Architecture is proposed in this paper.
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Flexible Real-time Embedded Architecture for Advanced Service Robots
2008Co-Authors: David Ramada, Houcine Hassan, C. Dominguez, A. CrespoAbstract:In most advanced real-time control applications such as service robots, the tasks have different criticality, flexible timing constraints and variable execution time. For instance, autonomous service robots perform their activities in dynamic environments, share resources and have to cooperate to fulfill their objectives. These changing environmental conditions produce a variability of the system load. Firstly, the computational requirements of recognition tasks are variable and dependent on the number of objects perceived in scenes. Secondly, the application processes are executed at different frequencies with varying periods and deadlines that are dependent on robot speeds. To tackle these aspects a flexible real-time Architecture is implemented in rt-linux in this paper. Moreover, the Architecture permits to extract the slack time, enabled in the system due to load variability, and to invest it in improving the communication performances of the robots. Experimental evaluations of the Architecture have been carried out with real autonomous robots.
Paul Sultana - One of the best experts on this subject based on the ideXlab platform.
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Synchroscalar: Initial lessons in power-aware design of a tile-based Embedded Architecture
Lecture Notes in Computer Science, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.
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PACS - Synchroscalar: initial lessons in power-aware design of a tile-based Embedded Architecture
Power-Aware Computer Systems, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.
Jedidiah R. Crandall - One of the best experts on this subject based on the ideXlab platform.
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Synchroscalar: Initial lessons in power-aware design of a tile-based Embedded Architecture
Lecture Notes in Computer Science, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.
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PACS - Synchroscalar: initial lessons in power-aware design of a tile-based Embedded Architecture
Power-Aware Computer Systems, 2005Co-Authors: John W. K. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. ChongAbstract:Embedded devices have hard performance targets and severe power and area constraints that depart significantly from our design intuitions derived from general-purpose microprocessor design. This paper describes our initial experiences in designing Synchroscalar, a tile-based Embedded Architecture targeted for multi-rate signal processing applications. We present a preliminary design of the Synchroscalar Architecture and some design space exploration in the context of important signal processing kernels. In particular, we find that synchronous design and substantial global interconnect are desirable in the low-frequency, low-power domain. This global interconnect enables parallelization and reduces processor idle time, which are critical to energy efficient implementations of high bandwidth signal processing. Furthermore, statically-scheduled communication and SIMD computation keep control overheads low and energy efficiency high.