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Yuefeng Ji - One of the best experts on this subject based on the ideXlab platform.

Yunxiang Fu - One of the best experts on this subject based on the ideXlab platform.

Liam Mcdaid - One of the best experts on this subject based on the ideXlab platform.

  • Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network
    Neural Processing Letters, 2013
    Co-Authors: Sandeep Pande, Seamus Cawley, Tom Bruintjes, Snaider Carrillo, Gerard Smit, Jim Harkin, Brian Mcginley, Fearghal Morgan, Liam Mcdaid
    Abstract:

    Biologically-inspired packet switched network on chip (NoC) based Hardware spiking neural network (SNN) architectures have been proposed as an Embedded computing platform for classification, estimation and control applications. Storage of large synaptic connectivity (SNN topology) information in SNNs require large distributed on-chip memory, which poses serious challenges for compact Hardware implementation of such architectures. Based on the structured neural organisation observed in human brain, a modular neural networks (MNN) design strategy partitions complex application tasks into smaller subtasks executing on distinct neural network modules, and integrates intermediate outputs in higher level functions. This paper proposes a Hardware modular neural tile (MNT) architecture that reduces the SNN topology memory requirement of NoC-based Hardware SNNs by using a combination of fixed and configurable synaptic connections. The proposed MNT contains a 16:16 fully-connected feed-forward SNN structure and integrates in a mesh topology NoC communication infrastructure. The SNN topology memory requirement is 50 % of the monolithic NoC-based Hardware SNN implementation. The paper also presents a lookup table based SNN topology memory allocation technique, which further increases the memory utilisation efficiency. Overall the area requirement of the architecture is reduced by an average of 66 % for practical SNN application topologies. The paper presents micro-architecture details of the proposed MNT and digital neuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65 nm low-power CMOS technology. The evolvable capability of the proposed MNT and its suitability for executing subtasks within a MNN execution architecture is demonstrated by successfully evolving benchmark SNN application tasks representing classification and non-linear control functions. The paper addresses Hardware modular SNN design and implementation challenges and contributes to the development of a compact Hardware modular SNN architecture suitable for Embedded applications

  • Modular neural tile architecture for compact Embedded Hardware spiking neural network
    Neural Processing Letters, 2013
    Co-Authors: Sandeep Pande, Seamus Cawley, Tom Bruintjes, Snaider Carrillo, Gerard Smit, Jim Harkin, Brian Mcginley, Fearghal Morgan, Liam Mcdaid
    Abstract:

    Biologically-inspired packet switched network on chip (NoC) based Hardware spiking neural network (SNN) architectures have been proposed as an Embedded computing platform for classification, estimation and control applications. Storage of large synaptic connectivity (SNN topology) information in SNNs require large distributed on-chip memory, which poses serious challenges for compact Hardware implementation of such architectures. Based on the structured neural organisation observed in human brain, a modular neural networks (MNN) design strategy partitions complex application tasks into smaller subtasks executing on distinct neural network modules, and integrates intermediate outputs in higher level functions. This paper proposes a Hardware modular neural tile (MNT) architecture that reduces the SNN topology memory requirement of NoC-based Hardware SNNs by using a combination of fixed and configurable synaptic connections. The proposed MNT contains a 16:16 fully-connected feed-forward SNN structure and integrates in a mesh topology NoC communication infrastructure. The SNN topology memory requirement is 50 % of the monolithic NoC-based Hardware SNN implementation. The paper also presents a lookup table based SNN topology memory allocation technique, which further increases the memory utilisation efficiency. Overall the area requirement of the architecture is reduced by an average of 66 % for practical SNN application topologies. The paper presents micro-architecture details of the proposed MNT and digital neuron circuit. The proposed architecture has been validated on a Xilinx Virtex-6 FPGA and synthesised using 65 nm low-power CMOS technology. The evolvable capability of the proposed MNT and its suitability for executing subtasks within a MNN execution architecture is demonstrated by successfully evolving benchmark SNN application tasks representing classification and non-linear control functions. The paper addresses Hardware modular SNN design and implementation challenges and contributes to the development of a compact Hardware modular SNN architecture suitable for Embedded applications © 2012 Springer Science+Business Media New York.

Rentao Gu - One of the best experts on this subject based on the ideXlab platform.

Hakima Chaouchi - One of the best experts on this subject based on the ideXlab platform.

  • RFID service for non-RFID enabled devices: Embedded Hardware implementation
    The 2nd International Conference on Ambient Systems Networks and Technologies (ANT), 2011
    Co-Authors: Oscar Botero, Hakima Chaouchi
    Abstract:

    Radio Frequency Identification (RFID) applications require the use of specialized Hardware in order to obtain the IDs that are provided by the tags. This condition limits the extension of the information to devices with non-RFID capabilities. In this paper we present the design and implementation of a RFID service conceived for devices with non-RFID Hardware but a WLAN interface. More specifically, we utilized Embedded Hardware to build an affordable and practical device that allows obtaining lists of tag IDs by using a common WLAN interface. Additionally, we performed delay metrics experiments and measurements are provided.

  • ANT/MobiWIS - RFID service for non-RFID enabled devices: Embedded Hardware implementation
    Procedia Computer Science, 2011
    Co-Authors: Oscar Botero, Hakima Chaouchi
    Abstract:

    Abstract Radio Frequency Identification (RFID) applications require the use of specialized Hardware in order to obtain the IDs that are provided by the tags. This condition limits the extension of the information to devices with non-RFID capabilities. In this paper we present the design and implementation of a RFID service conceived for devices with non-RFID Hardware but a WLAN interface. More specifically, we utilized Embedded Hardware to build an affordable and practical device that allows obtaining lists of tag IDs by using a common WLAN interface. Additionally, we performed delay metrics experiments and measurements are provided.