The Experts below are selected from a list of 22485 Experts worldwide ranked by ideXlab platform
Karam S. Chatha - One of the best experts on this subject based on the ideXlab platform.
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System level power and thermal management on Embedded Processors
2012Co-Authors: Karam S. Chatha, Sushu ZhangAbstract:Semiconductor scaling technology has led to a sharp growth in transistor counts. This has resulted in an exponential increase on both power dissipation and heat flux (or power density) in modern microProcessors. These microProcessors are integrated as the major components in many modern Embedded devices, which offer richer features and attain higher performance than ever before. Therefore, power and thermal management have become the significant design considerations for modern Embedded devices. Dynamic voltage/frequency scaling (DVFS) and dynamic power management (DPM) are two well-known hardware capabilities offered by modern Embedded Processors. However, the power or thermal aware performance optimization is not fully explored for the mainstream Embedded Processors with discrete DVFS and DPM capabilities. Many key problems have not been answered yet. What is the maximum performance that an Embedded processor can achieve under power or thermal constraint for a periodic application? Does there exist an efficient algorithm for the power or thermal management problems with guaranteed quality bound? These questions are hard to be answered because the discrete settings of DVFS and DPM enhance the complexity of many power and thermal management problems, which are generally NP-hard. The dissertation presents a comprehensive study on these NP-hard power and thermal management problems for Embedded Processors with discrete DVFS and DPM capabilities. In the domain of power management, the dissertation addresses the power minimization problem for real-time schedules, the energy-constrained make-span minimization problem on homogeneous and heterogeneous chip multiProcessors (CMP) architectures, and the battery aware energy management problem with nonlinear battery discharging model. In the domain of thermal management, the work addresses several thermal-constrained performance maximization problems for periodic Embedded applications. All the addressed problems are proved to be NP-hard or strongly NP-hard in the study. Then the work focuses on the design of the off-line optimal or polynomial time approximation algorithms as solutions in the problem design space. Several addressed NP-hard problems are tackled by dynamic programming with optimal solutions and pseudo-polynomial run time complexity. Because the optimal algorithms are not efficient in worst case, the fully polynomial time approximation algorithms are provided as more efficient solutions. Some efficient heuristic algorithms are also presented as solutions to several addressed problems. The comprehensive study answers the key questions in order to fully explore the power and thermal management potentials on Embedded Processors with discrete DVFS and DPM capabilities. The provided solutions enable the theoretical analysis of the maximum performance for periodic Embedded applications under power or thermal constraints.
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a performance model and code overlay generator for scratchpad enhanced Embedded Processors
International Conference on Hardware Software Codesign and System Synthesis, 2010Co-Authors: Michael A Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. ChathaAbstract:Software managed scratchpad memories (SPMs) provide improved performance and power in Embedded Processors by reducing required hardware resources. Performance depends strongly on the scheme used to map code and data onto the SPM, but generating optimal mappings can be extremely difficult. Here we address instruction mapping on SPMs and present a performance model and algorithm, "Code Overlay Generator" (COG), for producing high performance dynamic SPM code mappings. Our heuristic does not require profiling information, and is suitable for generating mapping solutions for large programs which are otherwise infeasible using previously proposed Integer Linear Programming (ILP) techniques. We compare our algorithm with a published heuristic and the code overlay mapping algorithm provided with the Cell Broadband Engine (CBE) Synergistic Processing Unit (SPU) compiler from IBM, spu-gcc. We find an average performance advantage of 34% compared to the previous algorithm, and 87% with respect to spugcc. We additionally show that our performance model enables improved tools for offline evaluation of code overlay performance and mapping selection.
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ICCAD - Scheduling of synchronous data flow models on scratchpad memory based Embedded Processors
2010 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2010Co-Authors: Weijia Che, Karam S. ChathaAbstract:Many Embedded Processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many Embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based Processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.
Weijia Che - One of the best experts on this subject based on the ideXlab platform.
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Scheduling of synchronous data flow models on scratchpad memory based Embedded Processors
IEEE ACM International Conference on Computer-Aided Design Digest of Technical Papers ICCAD, 2010Co-Authors: Weijia Che, Karamvir S. ChathaAbstract:Many Embedded Processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many Embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based Processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.
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ICCAD - Scheduling of synchronous data flow models on scratchpad memory based Embedded Processors
2010 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2010Co-Authors: Weijia Che, Karam S. ChathaAbstract:Many Embedded Processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many Embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based Processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.
Dimitris Gizopoulos - One of the best experts on this subject based on the ideXlab platform.
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Software-based self-testing of Embedded Processors
Processor Design: System-on-Chip Computing for ASICs and FPGAs, 2007Co-Authors: Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, George XenoulisAbstract:Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for Embedded Processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software- based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.
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effective software based self test strategies for on line periodic testing of Embedded Processors
Design Automation and Test in Europe, 2004Co-Authors: Antonis Paschalis, Dimitris GizopoulosAbstract:Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply Embedded Processors in low-cost Embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, software, or time redundancy mechanisms. In this paper, first, we identify the stringent characteristics of an SBST test program to be suitable for on-line periodic testing. Then, we introduce a new SBST methodology with a new classification scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for a RISC pipeline processor.
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Effective software-based self-test strategies for on-line periodic testing of Embedded Processors
Proceedings - Design Automation and Test in Europe Conference and Exhibition, 2004Co-Authors: Antonis Paschalis, Dimitris GizopoulosAbstract:Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply Embedded Processors in low-cost Embedded systems with respect to permanent and intermittent operational faults. Such strategies are well suited to Embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, information, software, or time-redundancy mechanisms. We first identify the stringent characteristics of a SBST program to be suitable for on-line periodic testing. Also, we study the probability for a SBST program to detect permanent and intermittent faults during on-line periodic testing. Then, we introduce a new SBST methodology with a new classification and test-priority scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for two pipeline reduced instruction set computers reduced instruction set Processors of different architecture.
Karamvir S. Chatha - One of the best experts on this subject based on the ideXlab platform.
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Scheduling of synchronous data flow models on scratchpad memory based Embedded Processors
IEEE ACM International Conference on Computer-Aided Design Digest of Technical Papers ICCAD, 2010Co-Authors: Weijia Che, Karamvir S. ChathaAbstract:Many Embedded Processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many Embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based Processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.
Antonis Paschalis - One of the best experts on this subject based on the ideXlab platform.
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Software-based self-testing of Embedded Processors
Processor Design: System-on-Chip Computing for ASICs and FPGAs, 2007Co-Authors: Nektarios Kranitis, Antonis Paschalis, Dimitris Gizopoulos, George XenoulisAbstract:Embedded processor testing techniques based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a nonintrusive testing approach and provides at-speed testing capability without any hardware or performance overheads. In this paper, we first present a high-level, functional component-oriented, software-based self-testing methodology for Embedded Processors. The proposed methodology aims at high structural fault coverage with low test development and test application cost. Then, we validate the effectiveness of the proposed methodology as a low-cost alternative over structural software- based self-testing methodologies based on automatic test pattern generation and pseudorandom testing. Finally, we demonstrate the effectiveness and efficiency of the proposed methodology by completely applying it on two different processor implementations of a popular RISC instruction set architecture including several gate-level implementations.
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effective software based self test strategies for on line periodic testing of Embedded Processors
Design Automation and Test in Europe, 2004Co-Authors: Antonis Paschalis, Dimitris GizopoulosAbstract:Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply Embedded Processors in low-cost Embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, software, or time redundancy mechanisms. In this paper, first, we identify the stringent characteristics of an SBST test program to be suitable for on-line periodic testing. Then, we introduce a new SBST methodology with a new classification scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for a RISC pipeline processor.
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Effective software-based self-test strategies for on-line periodic testing of Embedded Processors
Proceedings - Design Automation and Test in Europe Conference and Exhibition, 2004Co-Authors: Antonis Paschalis, Dimitris GizopoulosAbstract:Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply Embedded Processors in low-cost Embedded systems with respect to permanent and intermittent operational faults. Such strategies are well suited to Embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, information, software, or time-redundancy mechanisms. We first identify the stringent characteristics of a SBST program to be suitable for on-line periodic testing. Also, we study the probability for a SBST program to detect permanent and intermittent faults during on-line periodic testing. Then, we introduce a new SBST methodology with a new classification and test-priority scheme for processor components. After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for two pipeline reduced instruction set computers reduced instruction set Processors of different architecture.