The Experts below are selected from a list of 105 Experts worldwide ranked by ideXlab platform

R. Govindarajan - One of the best experts on this subject based on the ideXlab platform.

  • Memory Architecture Exploration Framework for Cache Based Embedded SOC
    21st International Conference on VLSI Design (VLSID 2008), 2008
    Co-Authors: T.s. Rajesh Kumar, C.p. Ravikumar, R. Govindarajan
    Abstract:

    Today's feature-rich multimedia products require Embedded System solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the Embedded System strongly influences critical System design objectives like area, power and performance. Hence the Embedded System Designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the Designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 Embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

  • MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
    20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
    Co-Authors: T.s. Rajesh Kumar, C.p. Ravikumar, R. Govindarajan
    Abstract:

    Today's feature-rich multimedia products require Embedded System solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the Embedded System strongly influences these parameters. Hence the Embedded System Designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the Designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 Embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop

T.s. Rajesh Kumar - One of the best experts on this subject based on the ideXlab platform.

  • Memory Architecture Exploration Framework for Cache Based Embedded SOC
    21st International Conference on VLSI Design (VLSID 2008), 2008
    Co-Authors: T.s. Rajesh Kumar, C.p. Ravikumar, R. Govindarajan
    Abstract:

    Today's feature-rich multimedia products require Embedded System solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the Embedded System strongly influences critical System design objectives like area, power and performance. Hence the Embedded System Designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the Designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 Embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

  • MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
    20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
    Co-Authors: T.s. Rajesh Kumar, C.p. Ravikumar, R. Govindarajan
    Abstract:

    Today's feature-rich multimedia products require Embedded System solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the Embedded System strongly influences these parameters. Hence the Embedded System Designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the Designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 Embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop

Francky Catthoor - One of the best experts on this subject based on the ideXlab platform.

  • A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
    Design Automation Conference, 2010
    Co-Authors: Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy De Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor
    Abstract:

    The key characteristic of next generation Embedded applications will be the intensive data transfer and storage and the need for efficient memory management. The Embedded System Designer community needs optimization methodologies and techniques, which do not change the input-output functionality of the software applications or the design of the underlying hardware platform. In this paper, the key focus is the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the data memory hierarchy of an MPSoC platform. We propose a design tool framework to efficiently automate the time-consuming optimizations for parallelization and memory mapping of static and dynamic data for MPSoCs.

  • DAC - A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms
    Proceedings of the 47th Design Automation Conference on - DAC '10, 2010
    Co-Authors: Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy De Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor
    Abstract:

    The key characteristic of next generation Embedded applications will be the intensive data transfer and storage and the need for efficient memory management. The Embedded System Designer community needs optimization methodologies and techniques, which do not change the input-output functionality of the software applications or the design of the underlying hardware platform. In this paper, the key focus is the efficient data access and memory storage of both dynamically and statically allocated data and their assignment on the data memory hierarchy of an MPSoC platform. We propose a design tool framework to efficiently automate the time-consuming optimizations for parallelization and memory mapping of static and dynamic data for MPSoCs.

Hoh Peter In - One of the best experts on this subject based on the ideXlab platform.

  • SNPD - Customer Value-based HW/SW Partitioning Decision in Embedded Systems
    2008 Ninth ACIS International Conference on Software Engineering Artificial Intelligence Networking and Parallel Distributed Computing, 2008
    Co-Authors: Hoh Peter In
    Abstract:

    In launching a product, requirement change is always risk to an Embedded System Designer. Including requirements change, limited resources (e.g. development time and cost) are also risk factors to designing a System. However, the time to market constraint among several limitations is most critical especially to Embedded System products (e.g. cellular phone, PDA, etc.). For that reason, many strategy makers try to find effective way to a HW/SW partitioning decision in early designing phase. Only ideal way to reduce requirements change and satisfy customers is reflecting their value to decision making steps in early phase prior to fixing HW and SW component design. In this paper, Customer Value based Partitioning Decision (CVPD) method is proposed to identify, analyze, and calculate the value of the customerspsila requirements, reflecting the value on the partitioning decision making process.

  • Customer Value-based HW/SW Partitioning Decision in Embedded Systems
    2008 Ninth ACIS International Conference on Software Engineering Artificial Intelligence Networking and Parallel Distributed Computing, 2008
    Co-Authors: Hoh Peter In
    Abstract:

    In launching a product, requirement change is always risk to an Embedded System Designer. Including requirements change, limited resources (e.g. development time and cost) are also risk factors to designing a System. However, the time to market constraint among several limitations is most critical especially to Embedded System products (e.g. cellular phone, PDA, etc.). For that reason, many strategy makers try to find effective way to a HW/SW partitioning decision in early designing phase. Only ideal way to reduce requirements change and satisfy customers is reflecting their value to decision making steps in early phase prior to fixing HW and SW component design. In this paper, Customer Value based Partitioning Decision (CVPD) method is proposed to identify, analyze, and calculate the value of the customerspsila requirements, reflecting the value on the partitioning decision making process.

C.p. Ravikumar - One of the best experts on this subject based on the ideXlab platform.

  • Memory Architecture Exploration Framework for Cache Based Embedded SOC
    21st International Conference on VLSI Design (VLSID 2008), 2008
    Co-Authors: T.s. Rajesh Kumar, C.p. Ravikumar, R. Govindarajan
    Abstract:

    Today's feature-rich multimedia products require Embedded System solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the Embedded System strongly influences critical System design objectives like area, power and performance. Hence the Embedded System Designer performs a complete memory architecture exploration to custom design a memory architecture for a given set of applications. Further, the Designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of exhaustive-search based memory exploration at the outer level and a two step based integrated data layout for SPRAM-Cache based architectures at the inner level. We present a two step integrated approach for data layout for SPRAM-Cache based hybrid architectures with the first step as data-partitioning that partitions data between SPRAM and Cache, and the second step is the cache conscious data layout. We formulate the cache-conscious data layout as a graph partitioning problem and show that our approach gives up to 34% improvement over an existing approach and also optimizes the off-chip memory address space. We experimented our approach with 3 Embedded multimedia applications and our approach explores several hundred memory configurations for each application, yielding several optimal design points in a few hours of computation on a standard desktop.

  • MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip
    20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), 2007
    Co-Authors: T.s. Rajesh Kumar, C.p. Ravikumar, R. Govindarajan
    Abstract:

    Today's feature-rich multimedia products require Embedded System solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the Embedded System strongly influences these parameters. Hence the Embedded System Designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the Designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 Embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop