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Zhuo Yang - One of the best experts on this subject based on the ideXlab platform.

  • 1200 V FS-IGBT with electric field modulation layer to improve trade-off between avalanche ruggedness and on-state voltage drop
    Electronics Letters, 2017
    Co-Authors: Zhuo Yang, Ye Tian, Fangjuan Bian, Xin Tong, Peng Ye
    Abstract:

    In this Letter, a novel 1200 V FS- insulated gate bipolar transistors (IGBT) is proposed to improve the trade-off between avalanche ruggedness and on-state voltage drop. The proposed IGBT features the high doping and thin n-layer under trench gates and we call it the electric field modulation layer (EFM layer). Under the avalanche condition, the EFM layer can form the sharp electric filed distribution in the EFM layer and the avalanche multiplication is constrained in the thin EFM layer. The difference between the holes and electrons due to the avalanche multiplication effect at the Emitter Side of the IGBT is minished. Therefore, the negative difference resistance in the avalanche I-V curve caused by the difference between the holes and electrons is eliminated. As a consequence, the avalanche ruggedness of the EFM-IGBT is improved. In the on-state, the high doping EFM layer can store the carriers and the on-state voltage drop of the EFM-IGBT is reduced to 1.48 V at 200 A/cm2. Finally, the EFM-IGBT improves the trade-off between avalanche ruggedness and on-state voltage drop.

  • A composite structure named self-adjusted conductivity modulation SOI-LIGBT with low on-state voltage
    2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), 2017
    Co-Authors: Weifeng Sun, Zhuo Yang, Jing Zhu, Ye Tian, Fangjuan Bian, Xin Tong, Sen Zhang
    Abstract:

    A composite device structure on Silicon-On-Insulator (SOI) layer named Self-adjust Conductivity Modulation SOI-LIGBT (SCM-LIGBT) is proposed. It can be divided into three parts: the normal LIGBT region (NLT structure), the EM-NMOS region (ENM structure) and the diode region (DIO structure). The drain of the ENM structure is connected with the n+ Emitter of the NLT structure while the p+ region in the Emitter Side of the NLT structure is connected to the anode of the DIO structure. The gates of the NLT structure and the ENM structure are connected together and they acted as the gate of the proposed SCM-LIGBT structure. In the on-state, the NPN parasitic bipolar structure of the NLT structure is triggered and the conductivity modulation is dramatically enhanced, which leads to the reduction on the on-state voltage. In addition, due to the base voltage of the NPN parasitic bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe-operating-area (FBSOA). The experiments demonstrate that the proposed SCM-LIGBT achieves the Vf lower than 1.18V at J A =150A/cm2.

  • High-Voltage Electron Injection Enhanced TC-LIGBT on 1.5- $\mu \text{m}$ -Thin SOI Layer for Reducing the Forward Voltage Drop
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Zhuo Yang, Hui Yu, Jincheng Zhou
    Abstract:

    In this paper, a new high-voltage electron injection enhanced tridimensional channel lateral insulated gate bipolar transistor (EIETC-LIGBT) on 1.5- $\mu \text{m}$ -thin silicon-on-insulator (SOI) layer is proposed to reduce the forward voltage drop. Based on the previous TC-LIGBT we have proposed, an extra floating p-layer is added at the Emitter Side of the proposed EIETC-LIGBT. The region locating between the separated p-body cells and the floating p-layer is the high doped n-type electron injection efficiency modulation (EIEM) region. Above the EIEM region, several virtual polygate structures connected to the Emitter are fabricated between the separated p-body cells and the floating p-layer. The highly doped EIEM region can help the proposed structure to reduce the forward voltage drop by increasing the electron injection efficiency. The virtual gate structures are contributed to the forward-biased safe operating area of the proposed structure. By optimizing the doping of the EIEM region and the width of the virtual gate structures, an EIETC-LIGBT with the forward voltage drop of 3.4 V at $V_{\mathrm {{GE}}}= 10$ V and $J_{\mathrm {{CE}}}= 100$ A/cm $^{\mathrm {{2}}}$ can be achieved, which has an improvement of 17% compared with the previous TC-LIGBT structure on the same thin SOI layer without sacrificing the current capability.

  • high voltage electron injection enhanced tc ligbt on 1 5 mu text m thin soi layer for reducing the forward voltage drop
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Zhuo Yang, Hui Yu, Jincheng Zhou
    Abstract:

    In this paper, a new high-voltage electron injection enhanced tridimensional channel lateral insulated gate bipolar transistor (EIETC-LIGBT) on 1.5- $\mu \text{m}$ -thin silicon-on-insulator (SOI) layer is proposed to reduce the forward voltage drop. Based on the previous TC-LIGBT we have proposed, an extra floating p-layer is added at the Emitter Side of the proposed EIETC-LIGBT. The region locating between the separated p-body cells and the floating p-layer is the high doped n-type electron injection efficiency modulation (EIEM) region. Above the EIEM region, several virtual polygate structures connected to the Emitter are fabricated between the separated p-body cells and the floating p-layer. The highly doped EIEM region can help the proposed structure to reduce the forward voltage drop by increasing the electron injection efficiency. The virtual gate structures are contributed to the forward-biased safe operating area of the proposed structure. By optimizing the doping of the EIEM region and the width of the virtual gate structures, an EIETC-LIGBT with the forward voltage drop of 3.4 V at $V_{\mathrm {{GE}}}= 10$ V and $J_{\mathrm {{CE}}}= 100$ A/cm $^{\mathrm {{2}}}$ can be achieved, which has an improvement of 17% compared with the previous TC-LIGBT structure on the same thin SOI layer without sacrificing the current capability.

  • A low loss IGBT with shallow p-well to adjust the carrier profiles at the Emitter Side
    2016 28th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2016
    Co-Authors: Zhuo Yang, Weifeng Sun Jing Zhu, Jingcheng Zhou, Zhu Yuanzheng
    Abstract:

    In this paper, a IGBT with Shallow P-well region at the Emitter Side (SP-IGBT) is proposed and compared with the Injection Enhanced Gate control Transistor (IEGT). The proposed SP-IGBT structure features that there are numerous shallow p-wells locate between the segmented p-body regions. Meanwhile, the shallow p-wells are covered by the planar poly gate. As a consequence, there exist many parasitic ‘depletion PMOSs’, and the PMOSs is also controlled by the gate. By optimizing the threshold voltage and the saturated current of the PMOSs, the carriers density in the drift region can be adjusted with high value during the on-state and low value during the turn-off process, which effectively improves the trade-off between the Eoff and the VCE, SAT. The SP-IGBT has been demonstrated by the simulations and experiments. The experiments results show that, with the blocking voltage of 1350V, the SP-IGBT structure achieves the VCESAT of 1.6V when the gate voltage VGE is 15V at the current density of 300A/cm2, while the Eoff is 24mJ/cm2. Compared with the conventional trench IEGT, the Eoff is improved by about 42% with the same VCE, SAT.

Weifeng Sun - One of the best experts on this subject based on the ideXlab platform.

  • A Novel Reverse Conducting SOI-LIGBT with Double Integrated NMOS for Enhanced Reverse Recovery
    2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), 2019
    Co-Authors: Long Zhang, Jing Zhu, Tian Tian, Yanqin Zou, Guichuang Zhu, Weifeng Sun
    Abstract:

    The reverse recovery failure of the inherent diode in Separated-Shorted-Anode lateral insulated gate bipolar transistor (SSA-LIGBT) is investigated through Sentaurus TCAD. During reverse recovery process, high current commutating rate di/dt will result in large reverse recovery current peak. It is found that large reverse recovery current peak flowing through the P-body can easily trigger the parasitic NPN transistor at the Emitter Side. Subsequently, the triggered NPN transistor finally results in the reverse recovery failure of the inherent diode in SSA-LIGBT. A novel structure with double integrated NMOS is proposed to achieve high reverse recovery robustness. Furthermore, the new structure can eliminate Negative Differential Resistance regime completely at the same time.

  • Influence of Emitter-Side Deep-oxide Trenches on Dynamic Avalanche Capability of SOI Lateral IGBTs Used for Monolithic Power ICs
    2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018
    Co-Authors: Long Zhang, Jing Zhu, Shilin Cao, Siyang Liu, Weifeng Sun, Jianfeng Zhao, Sen Zhang
    Abstract:

    This paper investigates the influence of Emitter-Side deep-oxide trenches (EDOT) on dynamic avalanche capability of SOI lateral IGBTs. The EDOT can modulate the electric filed (E-field) and carrier distributions under dynamic avalanche conditions. The enhanced electrons injection and strengthened Emitter-Side E-field result in wide positive differential resistance (PDR) branches. The reduced hole current density in the silicon region beneath the N+ Emitter contributes to high latch-up immunities. The hot spot at the edge of P-body can be weakened due to the suppressed impact ionization and alleviated carrier crowding. The wide PDR branch, high latch-up immunity and weak hot spot indicate an enhancement of dynamic avalanche capability, which is of great significance for monolithic power ICs operating under high voltage, high current, high dv/dt and/or high di/dt conditions.

  • A high-speed SOI-LIGBT with electric potential modulation trench and low-doped buried layer
    2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Qingxi Tang, Hao Wang, Ling Sun, Shikang Cheng, Sen Zhang
    Abstract:

    A high-voltage SOI-LIGBT with high turn-off speed and low turn-off loss (E OFF ) is proposed in this paper. The proposed SOI-LIGBT features a Low-doped Buried N-layer (LBN) region and an Emitter-Side Electric Potential Modulation Trench (EPMT) shorted with the P+ Emitter. By employing the LBN and EPMT, fast extraction of the stored carrier and the high turn-off speed are realized due to the accelerated depletion of N-drift region. The simulated results show that the proposed SOI-LIGBT can achieve a 73% lower turn-off loss compared with the conventional SOI-LIGBT at the same V ON of 1.52V. Moreover, the hole heat flux distribution in the proposed device predicts an improvement of ruggedness under high-voltage and high-current conditions.

  • Influence of Latch-Up Immunity Structure on ESD Robustness of SOI-LIGBT Used As Output Device
    IEEE Transactions on Device and Materials Reliability, 2018
    Co-Authors: Siyang Liu, Weifeng Sun, Ye Tian, Xue Ying, Feng Lin, Guipeng Sun, Yuwei Liu
    Abstract:

    The influences of three typical latch-up immunity structures, including high concentrated P++ doping layer, N+/P+ segmented Emitter and P-sink well, upon electro-static discharge (ESD) robustness of the silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) devices are compared. The high concentrated P++ doping layer makes the SOI-LIGBT have the weakest ESD robustness, because the slow turn-on speed of parasitic n-p-n transistor brings long-time high power state and heat accumulation. The N+/P+ segmented Emitter causes the SOI-LIGBT to own the medium ESD robustness and the SOI-LIGBT fails at the Emitter Side due to the crowded current made by the small N+ Emitter region. For the P-sink well, it makes SOI-LIGBT exhibit the strongest ESD robustness, because the current can flow along the P-sink into the Emitter vertically, which is helpful for reducing surface current density. ConSidering the comprehensive performances, the P-sink well is suggested as the latch-up immunity structure, which guarantees high latch-up immunity ability and strong ESD robustness simultaneously.

  • Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches
    IEEE Transactions on Electron Devices, 2017
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Minna Zhao, Jiajun Chen, Xuequan Huang, Longxing Shi, Jian Chen, Desheng Ding
    Abstract:

    A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the Emitter Side ( ${T}_{\textit {E}})$ and near the collector Side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the Emitter Side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector Side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

Jincheng Zhou - One of the best experts on this subject based on the ideXlab platform.

  • High-Voltage Electron Injection Enhanced TC-LIGBT on 1.5- $\mu \text{m}$ -Thin SOI Layer for Reducing the Forward Voltage Drop
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Zhuo Yang, Hui Yu, Jincheng Zhou
    Abstract:

    In this paper, a new high-voltage electron injection enhanced tridimensional channel lateral insulated gate bipolar transistor (EIETC-LIGBT) on 1.5- $\mu \text{m}$ -thin silicon-on-insulator (SOI) layer is proposed to reduce the forward voltage drop. Based on the previous TC-LIGBT we have proposed, an extra floating p-layer is added at the Emitter Side of the proposed EIETC-LIGBT. The region locating between the separated p-body cells and the floating p-layer is the high doped n-type electron injection efficiency modulation (EIEM) region. Above the EIEM region, several virtual polygate structures connected to the Emitter are fabricated between the separated p-body cells and the floating p-layer. The highly doped EIEM region can help the proposed structure to reduce the forward voltage drop by increasing the electron injection efficiency. The virtual gate structures are contributed to the forward-biased safe operating area of the proposed structure. By optimizing the doping of the EIEM region and the width of the virtual gate structures, an EIETC-LIGBT with the forward voltage drop of 3.4 V at $V_{\mathrm {{GE}}}= 10$ V and $J_{\mathrm {{CE}}}= 100$ A/cm $^{\mathrm {{2}}}$ can be achieved, which has an improvement of 17% compared with the previous TC-LIGBT structure on the same thin SOI layer without sacrificing the current capability.

  • high voltage electron injection enhanced tc ligbt on 1 5 mu text m thin soi layer for reducing the forward voltage drop
    IEEE Transactions on Electron Devices, 2016
    Co-Authors: Zhuo Yang, Hui Yu, Jincheng Zhou
    Abstract:

    In this paper, a new high-voltage electron injection enhanced tridimensional channel lateral insulated gate bipolar transistor (EIETC-LIGBT) on 1.5- $\mu \text{m}$ -thin silicon-on-insulator (SOI) layer is proposed to reduce the forward voltage drop. Based on the previous TC-LIGBT we have proposed, an extra floating p-layer is added at the Emitter Side of the proposed EIETC-LIGBT. The region locating between the separated p-body cells and the floating p-layer is the high doped n-type electron injection efficiency modulation (EIEM) region. Above the EIEM region, several virtual polygate structures connected to the Emitter are fabricated between the separated p-body cells and the floating p-layer. The highly doped EIEM region can help the proposed structure to reduce the forward voltage drop by increasing the electron injection efficiency. The virtual gate structures are contributed to the forward-biased safe operating area of the proposed structure. By optimizing the doping of the EIEM region and the width of the virtual gate structures, an EIETC-LIGBT with the forward voltage drop of 3.4 V at $V_{\mathrm {{GE}}}= 10$ V and $J_{\mathrm {{CE}}}= 100$ A/cm $^{\mathrm {{2}}}$ can be achieved, which has an improvement of 17% compared with the previous TC-LIGBT structure on the same thin SOI layer without sacrificing the current capability.

Long Zhang - One of the best experts on this subject based on the ideXlab platform.

  • A Novel Reverse Conducting SOI-LIGBT with Double Integrated NMOS for Enhanced Reverse Recovery
    2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), 2019
    Co-Authors: Long Zhang, Jing Zhu, Tian Tian, Yanqin Zou, Guichuang Zhu, Weifeng Sun
    Abstract:

    The reverse recovery failure of the inherent diode in Separated-Shorted-Anode lateral insulated gate bipolar transistor (SSA-LIGBT) is investigated through Sentaurus TCAD. During reverse recovery process, high current commutating rate di/dt will result in large reverse recovery current peak. It is found that large reverse recovery current peak flowing through the P-body can easily trigger the parasitic NPN transistor at the Emitter Side. Subsequently, the triggered NPN transistor finally results in the reverse recovery failure of the inherent diode in SSA-LIGBT. A novel structure with double integrated NMOS is proposed to achieve high reverse recovery robustness. Furthermore, the new structure can eliminate Negative Differential Resistance regime completely at the same time.

  • Influence of Emitter-Side Deep-oxide Trenches on Dynamic Avalanche Capability of SOI Lateral IGBTs Used for Monolithic Power ICs
    2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018
    Co-Authors: Long Zhang, Jing Zhu, Shilin Cao, Siyang Liu, Weifeng Sun, Jianfeng Zhao, Sen Zhang
    Abstract:

    This paper investigates the influence of Emitter-Side deep-oxide trenches (EDOT) on dynamic avalanche capability of SOI lateral IGBTs. The EDOT can modulate the electric filed (E-field) and carrier distributions under dynamic avalanche conditions. The enhanced electrons injection and strengthened Emitter-Side E-field result in wide positive differential resistance (PDR) branches. The reduced hole current density in the silicon region beneath the N+ Emitter contributes to high latch-up immunities. The hot spot at the edge of P-body can be weakened due to the suppressed impact ionization and alleviated carrier crowding. The wide PDR branch, high latch-up immunity and weak hot spot indicate an enhancement of dynamic avalanche capability, which is of great significance for monolithic power ICs operating under high voltage, high current, high dv/dt and/or high di/dt conditions.

  • A high-speed SOI-LIGBT with electric potential modulation trench and low-doped buried layer
    2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Qingxi Tang, Hao Wang, Ling Sun, Shikang Cheng, Sen Zhang
    Abstract:

    A high-voltage SOI-LIGBT with high turn-off speed and low turn-off loss (E OFF ) is proposed in this paper. The proposed SOI-LIGBT features a Low-doped Buried N-layer (LBN) region and an Emitter-Side Electric Potential Modulation Trench (EPMT) shorted with the P+ Emitter. By employing the LBN and EPMT, fast extraction of the stored carrier and the high turn-off speed are realized due to the accelerated depletion of N-drift region. The simulated results show that the proposed SOI-LIGBT can achieve a 73% lower turn-off loss compared with the conventional SOI-LIGBT at the same V ON of 1.52V. Moreover, the hole heat flux distribution in the proposed device predicts an improvement of ruggedness under high-voltage and high-current conditions.

  • Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches
    IEEE Transactions on Electron Devices, 2017
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Minna Zhao, Jiajun Chen, Xuequan Huang, Longxing Shi, Jian Chen, Desheng Ding
    Abstract:

    A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the Emitter Side ( ${T}_{\textit {E}})$ and near the collector Side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the Emitter Side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector Side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

  • U-shaped channel SOI-LIGBT with dual trenches to improve the trade-off between saturation voltage and turn-off loss
    2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), 2017
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Sen Zhang, Minna Zhao, Jiajun Chen, Xuequan Huang, Desheng Ding, Bo Hou
    Abstract:

    This paper proposes a 500V U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to improve the trade-off between the saturation voltage (V CEsat ) and the turn-off loss (E off ). The proposed dual trenches U-shaped channel (DTU) SOI-LIGBT features a U-shaped gate trench (Gl) and a U-shaped hole barrier trench (G2). By employing the dual trenches, enhanced carrier stored effect at the Emitter Side and more uniform carriers distribution in the drift region can be obtained, resulting in decreases of V CEsat and E off . By optimizing the dimensions of the U-shaped channel, it is found that the proposed DTU SOI-LIGBT can achieve a 52.3% lower E off compared with the planar gate U-shaped channel (PGU) SOI-LIGBT at the same V CEsat of 1.22 V.

Jing Zhu - One of the best experts on this subject based on the ideXlab platform.

  • A Novel Reverse Conducting SOI-LIGBT with Double Integrated NMOS for Enhanced Reverse Recovery
    2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), 2019
    Co-Authors: Long Zhang, Jing Zhu, Tian Tian, Yanqin Zou, Guichuang Zhu, Weifeng Sun
    Abstract:

    The reverse recovery failure of the inherent diode in Separated-Shorted-Anode lateral insulated gate bipolar transistor (SSA-LIGBT) is investigated through Sentaurus TCAD. During reverse recovery process, high current commutating rate di/dt will result in large reverse recovery current peak. It is found that large reverse recovery current peak flowing through the P-body can easily trigger the parasitic NPN transistor at the Emitter Side. Subsequently, the triggered NPN transistor finally results in the reverse recovery failure of the inherent diode in SSA-LIGBT. A novel structure with double integrated NMOS is proposed to achieve high reverse recovery robustness. Furthermore, the new structure can eliminate Negative Differential Resistance regime completely at the same time.

  • Influence of Emitter-Side Deep-oxide Trenches on Dynamic Avalanche Capability of SOI Lateral IGBTs Used for Monolithic Power ICs
    2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2018
    Co-Authors: Long Zhang, Jing Zhu, Shilin Cao, Siyang Liu, Weifeng Sun, Jianfeng Zhao, Sen Zhang
    Abstract:

    This paper investigates the influence of Emitter-Side deep-oxide trenches (EDOT) on dynamic avalanche capability of SOI lateral IGBTs. The EDOT can modulate the electric filed (E-field) and carrier distributions under dynamic avalanche conditions. The enhanced electrons injection and strengthened Emitter-Side E-field result in wide positive differential resistance (PDR) branches. The reduced hole current density in the silicon region beneath the N+ Emitter contributes to high latch-up immunities. The hot spot at the edge of P-body can be weakened due to the suppressed impact ionization and alleviated carrier crowding. The wide PDR branch, high latch-up immunity and weak hot spot indicate an enhancement of dynamic avalanche capability, which is of great significance for monolithic power ICs operating under high voltage, high current, high dv/dt and/or high di/dt conditions.

  • A high-speed SOI-LIGBT with electric potential modulation trench and low-doped buried layer
    2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2018
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Qingxi Tang, Hao Wang, Ling Sun, Shikang Cheng, Sen Zhang
    Abstract:

    A high-voltage SOI-LIGBT with high turn-off speed and low turn-off loss (E OFF ) is proposed in this paper. The proposed SOI-LIGBT features a Low-doped Buried N-layer (LBN) region and an Emitter-Side Electric Potential Modulation Trench (EPMT) shorted with the P+ Emitter. By employing the LBN and EPMT, fast extraction of the stored carrier and the high turn-off speed are realized due to the accelerated depletion of N-drift region. The simulated results show that the proposed SOI-LIGBT can achieve a 73% lower turn-off loss compared with the conventional SOI-LIGBT at the same V ON of 1.52V. Moreover, the hole heat flux distribution in the proposed device predicts an improvement of ruggedness under high-voltage and high-current conditions.

  • Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches
    IEEE Transactions on Electron Devices, 2017
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Minna Zhao, Jiajun Chen, Xuequan Huang, Longxing Shi, Jian Chen, Desheng Ding
    Abstract:

    A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the Emitter Side ( ${T}_{\textit {E}})$ and near the collector Side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the Emitter Side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector Side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

  • U-shaped channel SOI-LIGBT with dual trenches to improve the trade-off between saturation voltage and turn-off loss
    2017 29th International Symposium on Power Semiconductor Devices and IC's (ISPSD), 2017
    Co-Authors: Long Zhang, Jing Zhu, Weifeng Sun, Sen Zhang, Minna Zhao, Jiajun Chen, Xuequan Huang, Desheng Ding, Bo Hou
    Abstract:

    This paper proposes a 500V U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to improve the trade-off between the saturation voltage (V CEsat ) and the turn-off loss (E off ). The proposed dual trenches U-shaped channel (DTU) SOI-LIGBT features a U-shaped gate trench (Gl) and a U-shaped hole barrier trench (G2). By employing the dual trenches, enhanced carrier stored effect at the Emitter Side and more uniform carriers distribution in the drift region can be obtained, resulting in decreases of V CEsat and E off . By optimizing the dimensions of the U-shaped channel, it is found that the proposed DTU SOI-LIGBT can achieve a 52.3% lower E off compared with the planar gate U-shaped channel (PGU) SOI-LIGBT at the same V CEsat of 1.22 V.