The Experts below are selected from a list of 11661 Experts worldwide ranked by ideXlab platform
G Groeseneken - One of the best experts on this subject based on the ideXlab platform.
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Improved NBTI reliability with sub-1-nanometer EOT ZrO 2 gate dielectric compared with HfO 2
IEEE Electron Device Letters, 2013Co-Authors: Moonju Cho, Ben Kaczer, T Kauerauf, Lars Ake Ragnarsson, G GroesenekenAbstract:The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (ΔVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (ΔNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower ΔNit than HfO2 device. However, the ΔNit contribution to the total ΔVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric.
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Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions
Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2013Co-Authors: G Groeseneken, Ben Kaczer, Marc Aoulaiche, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Moonju Cho, Jacopo Franco, Jerome Mitard, Maria Toledano-luqueAbstract:In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.
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Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices
IEEE Transactions on Electron Devices, 2012Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Jae-duk Lee, Jacopo Franco, G GroesenekenAbstract:New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.
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interface trap characterization of a 5 8 hbox rm aa EOT p mosfet using high frequency on chip ring oscillator charge pumping technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
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Interface Trap Characterization of a 5.8- $\hbox{\rm{ \AA}}$ EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T. Y. Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
Lars Ake Ragnarsson - One of the best experts on this subject based on the ideXlab platform.
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Improved NBTI reliability with sub-1-nanometer EOT ZrO 2 gate dielectric compared with HfO 2
IEEE Electron Device Letters, 2013Co-Authors: Moonju Cho, Ben Kaczer, T Kauerauf, Lars Ake Ragnarsson, G GroesenekenAbstract:The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (ΔVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (ΔNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower ΔNit than HfO2 device. However, the ΔNit contribution to the total ΔVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric.
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Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions
Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2013Co-Authors: G Groeseneken, Ben Kaczer, Marc Aoulaiche, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Moonju Cho, Jacopo Franco, Jerome Mitard, Maria Toledano-luqueAbstract:In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.
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Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices
IEEE Transactions on Electron Devices, 2012Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Jae-duk Lee, Jacopo Franco, G GroesenekenAbstract:New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.
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interface trap characterization of a 5 8 hbox rm aa EOT p mosfet using high frequency on chip ring oscillator charge pumping technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
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Interface Trap Characterization of a 5.8- $\hbox{\rm{ \AA}}$ EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T. Y. Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
Ben Kaczer - One of the best experts on this subject based on the ideXlab platform.
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Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions
Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2013Co-Authors: G Groeseneken, Ben Kaczer, Marc Aoulaiche, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Moonju Cho, Jacopo Franco, Jerome Mitard, Maria Toledano-luqueAbstract:In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.
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Improved NBTI reliability with sub-1-nanometer EOT ZrO 2 gate dielectric compared with HfO 2
IEEE Electron Device Letters, 2013Co-Authors: Moonju Cho, Ben Kaczer, T Kauerauf, Lars Ake Ragnarsson, G GroesenekenAbstract:The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (ΔVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (ΔNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower ΔNit than HfO2 device. However, the ΔNit contribution to the total ΔVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric.
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Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices
IEEE Transactions on Electron Devices, 2012Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Jae-duk Lee, Jacopo Franco, G GroesenekenAbstract:New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.
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interface trap characterization of a 5 8 hbox rm aa EOT p mosfet using high frequency on chip ring oscillator charge pumping technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
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Towards 1X DRAM: Improved leakage 0.4 nm EOT STO-based MIMcap and explanation of leakage reduction mechanism showing further potential
2011Co-Authors: M. A. Pawlak, Ben Kaczer, Wan-chih Wang, Min-soo Kim, Mihaela Popovici, J. Swerts, K. Tomida, Karl Opsomer, Marc Schaekers, Christa VranckenAbstract:We establish a new record low leakage (J G )-EOT for DRAM compatible MIMcap by further J G reduction to 2×10−8 (10−7) A/cm2 at 0.45 (0.40) nm EOT (0.8 V) using an improved RuO x /TiO x /Sr-rich Sr x Ti y O z (STO) stack. Further, for the first time we provide insight explaining the origin of the record low J G -EOT achieved, by detailed studies of our TiO x /STO stack on TiN, Ru and RuO x bottom electrodes (BE). TiO x reduces EOT on all BE (without degrading microstructure), but RuO x is needed for low J G . We prove the latter is NOT due to a work function (WF) effect, measuring -on the contrary- strong Fermi Level Pinning (FLP) at STO midgap and same e-injection barrier (∼1.6 eV) from TiN, Ru or RuO x . We determine leakage is controlled by similar traps (∼0.8 eV below CBE) in STO for all stacks and BE, and attribute improvement with RuO x to local STO trap density reduction by eliminating (or even reversing) oxygen scavenging effects near the electrode during crystallization. We demonstrate the potential for further J G reduction by lowering trap density, with theoretical limit for trap-free STO of 10−15 A/cm2 at EOT∼0.4 nm. These results make STO a clear candidate for future DRAM.
Philippe Roussel - One of the best experts on this subject based on the ideXlab platform.
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Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions
Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2013Co-Authors: G Groeseneken, Ben Kaczer, Marc Aoulaiche, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Moonju Cho, Jacopo Franco, Jerome Mitard, Maria Toledano-luqueAbstract:In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.
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Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices
IEEE Transactions on Electron Devices, 2012Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Jae-duk Lee, Jacopo Franco, G GroesenekenAbstract:New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.
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interface trap characterization of a 5 8 hbox rm aa EOT p mosfet using high frequency on chip ring oscillator charge pumping technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
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Interface Trap Characterization of a 5.8- $\hbox{\rm{ \AA}}$ EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T. Y. Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
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positive and negative bias temperature instability on sub nanometer EOT high k mosfets
International Reliability Physics Symposium, 2010Co-Authors: Marc Aoulaiche, Ben Kaczer, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, Joshua Tseng, Thomas Hoffmann, G GroesenekenAbstract:For the first time, positive and negative bias temperature instability (P/NBTI) mechanisms in sub-nanometer EOT devices are investigated in this study. It is shown that PBTI degradation in sub-nanometer EOT devices occurs by interface degradation, additionally to the oxide bulk trap filling which is the dominant mechanism in over 1nm EOT devices. For NBTI, interface degradation remains as the main mechanism in sub-nano EOT devices, and additional high contribution of the high-k bulk defects can increase the degradation below 6A EOT.
T Kauerauf - One of the best experts on this subject based on the ideXlab platform.
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Improved NBTI reliability with sub-1-nanometer EOT ZrO 2 gate dielectric compared with HfO 2
IEEE Electron Device Letters, 2013Co-Authors: Moonju Cho, Ben Kaczer, T Kauerauf, Lars Ake Ragnarsson, G GroesenekenAbstract:The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (ΔVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (ΔNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower ΔNit than HfO2 device. However, the ΔNit contribution to the total ΔVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric.
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Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions
Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2013Co-Authors: G Groeseneken, Ben Kaczer, Marc Aoulaiche, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Moonju Cho, Jacopo Franco, Jerome Mitard, Maria Toledano-luqueAbstract:In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.
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Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices
IEEE Transactions on Electron Devices, 2012Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, T Kauerauf, Lars Ake Ragnarsson, Jae-duk Lee, Jacopo Franco, G GroesenekenAbstract:New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.
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interface trap characterization of a 5 8 hbox rm aa EOT p mosfet using high frequency on chip ring oscillator charge pumping technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.
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Interface Trap Characterization of a 5.8- $\hbox{\rm{ \AA}}$ EOT p-MOSFET Using High-Frequency On-Chip Ring Oscillator Charge Pumping Technique
IEEE Transactions on Electron Devices, 2011Co-Authors: Moonju Cho, Ben Kaczer, Marc Aoulaiche, Robin Degraeve, Philippe Roussel, J Franco, T Kauerauf, Lars Ake Ragnarsson, T. Y. Hoffmann, G GroesenekenAbstract:Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.