The Experts below are selected from a list of 42042 Experts worldwide ranked by ideXlab platform

Krishna C Mandal - One of the best experts on this subject based on the ideXlab platform.

  • characterization of deep levels in n type and semi insulating 4h sic Epitaxial Layers by thermally stimulated current spectroscopy
    Journal of Applied Physics, 2012
    Co-Authors: Peter G Muzykov, Ramesh M Krishna, Krishna C Mandal
    Abstract:

    We have investigated deep level centers in n-type and semi-insulating (SI) 4H-SiC Epitaxial Layers by thermally stimulated current (TSC) spectroscopy. The Epitaxial Layers were grown using chemical vapor deposition utilizing a dichlorosilane precursor. Both Epitaxial Layers exhibited relatively shallow levels related to Al, B, L- and D-centers. A deep level center with an activation energy of 1.1 eV, peaked at ∼400 K, was detected in the n-type Epitaxial Layer and correlated with the IL2 level and the 1.1 eV center in a high purity bulk SI 4H-SiC. The TSC spectra of the SI Epitaxial Layer was dominated by the peaks at 525–585 K that we attributed to intrinsic defects and their complexes with energy levels close to the middle of the bandgap. The TSC spectra of SI Epitaxial Layer exhibited peaks with different current polarity which is explained by thermoelectric effect and the built-in electric field reversal. The results of the transfer length method measurements of the SI Epitaxial Layer and the room tem...

Jef Poortmans - One of the best experts on this subject based on the ideXlab platform.

  • evaluation of the influence of an embedded porous silicon Layer on the bulk lifetime of Epitaxial Layers and the interface recombination at the Epitaxial Layer porous silicon interface
    Progress in Photovoltaics, 2014
    Co-Authors: Hariharsudan Sivaramakrishnan Radhakrishnan, Frederic Dross, Maarten Debucquoy, Philipp Rosenits, Kris Van Nieuwenhuysen, Ivan Gordon, Jef Poortmans
    Abstract:

    Porous silicon plays an important role in the concept of wafer-equivalent Epitaxial thin-film solar cells. Although porous silicon is beneficial in terms of long-wavelength optical confinement and gettering of metals, it could adversely affect the quality of the Epitaxial silicon Layer grown on top of it by introducing additional crystal defects such as stacking faults and dislocations. Furthermore, the Epitaxial Layer/porous silicon interface is highly recombinative because it has a large internal surface area that is not accessible for passivation. In this work, photoluminescence is used to extract the bulk lifetime of boron-doped (1016/cm3) Epitaxial Layers grown on reorganised porous silicon as well as on pristine mono-crystalline, Czochralski, p+ silicon. Surprisingly, the bulk lifetime of Epitaxial Layers on top of reorganised porous silicon is found to be higher (~100–115 µs) than that of Layers on top of bare p+ substrate (32–50 µs). It is believed that proper surface closure prior to Epitaxial growth and metal gettering effects of porous silicon play a role in ensuring a higher lifetime. Furthermore, the Epitaxial Layer/porous silicon interface was found to be ~250 times more recombinative than an Epitaxial Layer/p+ substrate interface (S ≅ 103 cm/s). However, the inclusion of an Epitaxially grown back surface field on top of the porous silicon effectively shields minority carriers from this highly recombinative interface. Copyright © 2013 John Wiley & Sons, Ltd.

Kazuo Arai - One of the best experts on this subject based on the ideXlab platform.

  • Silicon carbide Epitaxial Layer growths on Acheson seed crystals from silicon melt
    Materials Letters, 2002
    Co-Authors: M. Nasir Khan, Tomohisa Kato, Shin-ichi Nishizawa, Ryoji Kosugi, Kazuo Arai
    Abstract:

    Abstract Silicon carbide Epitaxial Layer growth was carried out on both Si- and C-faces of the 6H–SiC Acheson seed crystals by a technique similar to that used for the sublimation growth of bulk single crystals of this material. High-resolution XRD (HRXRD) measurements showed the single crystalline structure for these grown Layers. RHEED patterns confirmed that the grown Layers are of single crystalline nature having ( n × n ) surface reconstruction. Raman spectroscopy showed the same polytype for the grown Layers as that of the seed crystals. Atomic force and optical microscopy revealed smooth, uniform and mirror like surfaces for the grown Layers. Step flow growth mechanism was observed on both Si- and C-faces of the seed crystal. The grown Layers show similar characteristic features as that observed for the SiC Layers grown by other techniques such as liquid phase epitaxy (LPE) and chemical vapor deposition (CVD). The technique used is a simple, viable and new alternative for growing SiC Epitaxial Layers.

Su Guanchuang - One of the best experts on this subject based on the ideXlab platform.

  • method of preparing trench semiconductor power discrete device
    2013
    Co-Authors: Su Guanchuang
    Abstract:

    The invention discloses a method of preparing a trench semiconductor power discrete device. The method comprises the following steps of firstly injecting P-type doping agents into an Epitaxial Layer on a substrate through a trench mask to form P-type base regions, and then eroding the Epitaxial Layer to form a plurality of grid trenches; injecting N-type doping agents into side walls of the tops of the trenches to form N-type source regions; then, settlinginterLayer dielectric on the surface of the Epitaxial Layer, eroding the interLayer dielectric and the surface of the Epitaxial Layer to form contact trenches by means of a contact hole mask, and filling the contact trenches with metal plugs; and finally, settling a metal Layer on the upper surface of the device, and conducting metal erosion through a metal mask to form a metal cushion Layer and a connection line. By means of the preparing method, preparing processes of a base-region mask and a source-region mask are omitted, and therefore manufacturing cost of the device is greatly lowered; and meanwhile, original electrical characteristics of the device is not influenced, and therefore the price performance ratio of the device is increased.

  • preparation method of trench semiconductor power discrete device
    2013
    Co-Authors: Su Guanchuang
    Abstract:

    The invention discloses a preparation method of a trench semiconductor power discrete device. The preparation method of the trench semiconductor power discrete device includes a first step of injecting P-type dopant into an Epitaxial Layer arranged on a substrate to form P-type base regions through a trench mask and conducting corrosion on the Epitaxial Layer to form a plurality of grid trenches; a second step of depositing interLayer mediums on the Epitaxial Layer, conducting the corrosion on the interLayer mediums through a contact hole mask, forming trenches in the interLayer mediums, injecting N-type dopant to form N-type source regions, conducting the corrosion on the surface of the Epitaxial Layer to form contact trenches, and conducting metal plugging filling on the contact trenches; and a third step of depositing a metal Layer on the surface of the discrete device, conducting metal corrosion through a metal mask and forming a metal substrate Layer and a connecting wire. The preparation method of the trench semiconductor power discrete device eliminates preparation procedures of a base region mask and a source region mask, and therefore the manufacturing cost of the discrete device is greatly reduced. In addition, original electrical characteristics of the discrete device cannot be influenced.

Hervé Morel - One of the best experts on this subject based on the ideXlab platform.

  • Epitaxial Layer Parameters Estimation Approach of Silicon Carbide Schottky Diodes
    Sensor letters, 2009
    Co-Authors: Tarek Ben Salah, Mahbouba Amairi, Zina Sassi, Hervé Morel
    Abstract:

    Silicon-carbide Schottky diode is seen as one of the newest devices deployed in sensor application. Temperature sensors using these highly developed devices have been introduced. The linearity of the output signal versus temperature of the silicon-carbide Schottky diode is demonstrated. From a modeling point of view, accurate simulations are necessary for checking sensor behavior. These simulations tend to rely on component models and associated confidential Epitaxial parameters. Therefore, this paper sets out to extract accurate parameters of the silicon-carbide Schottky diode. In pursuit of this end, a systematic approach is developed and a physically based model is introduced. This model is run for many devices, giving directly Epitaxial Layer parameters. A contrastive study between experimental and simulation is undertaken, resulting in good agreement.

  • Experimental analysis of punch-through conditions in power P-I-N diodes
    IEEE Transactions on Power Electronics, 2007
    Co-Authors: Tarek Ben Salah, Sami Ghedira, Cyril Buttay, Hervé Morel, Bruno Allard, Kamel Besbes
    Abstract:

    Commercial power diodes are optimized to feature punch-through behavior. However, a tradeoff between the width and the doping level of the diode Epitaxial Layer leads to various levels of optimization. For a given breakdown voltage, a shorter Epitaxial Layer width leads to better transient performances. Device datasheets do not cover this issue and a simple experimental setup is presented to assess the optimization conditions inside the diode Epitaxial Layer. Three commercial devices are tested and experimental results are confronted to device simulations. A good agreement is found