The Experts below are selected from a list of 1419 Experts worldwide ranked by ideXlab platform

Georges Bremond - One of the best experts on this subject based on the ideXlab platform.

  • Study of deep traps in AlGaN/GaN high-electron mobility transistors by electrical characterization and simulation
    Journal of Applied Physics, 2019
    Co-Authors: Philippe Ferrandis, Mariam El-khatib, Marie-anne Jaud, Erwan Morvan, Matthew Charles, Gérard Guillot, Georges Bremond
    Abstract:

    The localization of deep traps in normally-off AlGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the Equipotential Line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a trap with an EC – 0.5 eV to ion etching induced damage.The localization of deep traps in normally-off AlGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the Equipotential Line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a t...

  • Study of deep traps in AlGaN/GaN high-electron mobility transistors by electrical characterization and simulation
    Journal of Applied Physics, 2019
    Co-Authors: Philippe Ferrandis, Mariam El-khatib, Marie-anne Jaud, Erwan Morvan, Matthew Charles, Gérard Guillot, Georges Bremond
    Abstract:

    The localization of deep traps in normally-off AlGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the Equipotential Line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a trap with an E C-0.5 eV to ion etching induced damage. Published under license by AIP Publishing. https://doi.

Philippe Ferrandis - One of the best experts on this subject based on the ideXlab platform.

  • Study of deep traps in AlGaN/GaN high-electron mobility transistors by electrical characterization and simulation
    Journal of Applied Physics, 2019
    Co-Authors: Philippe Ferrandis, Mariam El-khatib, Marie-anne Jaud, Erwan Morvan, Matthew Charles, Gérard Guillot, Georges Bremond
    Abstract:

    The localization of deep traps in normally-off AlGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the Equipotential Line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a trap with an EC – 0.5 eV to ion etching induced damage.The localization of deep traps in normally-off AlGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the Equipotential Line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a t...

  • Study of deep traps in AlGaN/GaN high-electron mobility transistors by electrical characterization and simulation
    Journal of Applied Physics, 2019
    Co-Authors: Philippe Ferrandis, Mariam El-khatib, Marie-anne Jaud, Erwan Morvan, Matthew Charles, Gérard Guillot, Georges Bremond
    Abstract:

    The localization of deep traps in normally-off AlGaN/GaN metal-oxide-semiconductor channel high-electron mobility transistors has been established by means of capacitance and current deep level transient spectroscopies (DLTS). Electrical simulations of the total current density between the drain and source contacts, the electron density, and the Equipotential Line distribution helped to understand the transport mechanisms into the device and to determine the zone probed by DLTS measurements. By changing the drain-source voltage in current DLTS or the reverse bias in capacitance DLTS, we demonstrated that we can choose to probe either the region below the gate or the region between the gate and drain electrodes. We could then see that defects related to reactive ion etching induced surface damage, expected to be formed during the gate recess process, were located only under the gate contact whereas native defects were found everywhere in the GaN layer. Thanks to this method of localization, we assigned a trap with an E C-0.5 eV to ion etching induced damage. Published under license by AIP Publishing. https://doi.

Hu Xian-quan - One of the best experts on this subject based on the ideXlab platform.

Ngai Kit Poon - One of the best experts on this subject based on the ideXlab platform.

  • common mode noise cancellation in switching mode power supplies using an Equipotential transformer modeling technique
    IEEE Transactions on Electromagnetic Compatibility, 2012
    Co-Authors: Yick Po Chan, Bryan Man Hay Pong, Ngai Kit Poon
    Abstract:

    Electromagnetic interference (EMI) is a significant challenge in the design of high-efficiency switching-mode power supplies due to the presence of common-mode (CM) noise. In many power-supply designs, a variety of noise suppression schemes must be implemented in order to meet EMI requirements. Most of these schemes create power loss that lead to efficiency and thermal issues. In this paper, a transformer construction technique is proposed that effectively reduces the CM noise current injecting across the isolated primary and secondary windings. This technique is based on the zero Equipotential Line theory. A transformer design with the proposed CM noise cancellation technique can achieve high conversion efficiency as well as substantial CM noise rejection.

  • Common-Mode Noise Cancellation in Switching-Mode Power Supplies Using an Equipotential Transformer Modeling Technique
    IEEE Transactions on Electromagnetic Compatibility, 2012
    Co-Authors: Yick Po Chan, Ngai Kit Poon, Bryan Man Hay Pong, J.c.p. Liu
    Abstract:

    Electromagnetic interference (EMI) is a significant challenge in the design of high-efficiency switching-mode power supplies due to the presence of common-mode (CM) noise. In many power-supply designs, a variety of noise suppression schemes must be implemented in order to meet EMI requirements. Most of these schemes create power loss that lead to efficiency and thermal issues. In this paper, a transformer construction technique is proposed that effectively reduces the CM noise current injecting across the isolated primary and secondary windings. This technique is based on the zero Equipotential Line theory. A transformer design with the proposed CM noise cancellation technique can achieve high conversion efficiency as well as substantial CM noise rejection.

  • Effective switching mode power supplies common mode noise cancellation technique with zero Equipotential transformer models
    2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010
    Co-Authors: Yick Po Chan, Man Hay Pong, Ngai Kit Poon
    Abstract:

    In this paper a transformer construction technique is proposed that effectively cut off the Common Mode (CM) noise voltage passing across the isolated primary and secondary windings. This technique employs the Zero Equipotential Line theory to construct an anti-phase winding. It effectively cuts down CM noise by eliminating the noise voltage across the isolated primary and secondary windings. The concept of maintaining an Equipotential Line along the bobbin and quiet node connections are justified by analysis. A well considered transformer design with the proposed CM noise cancellation technique can achieve high conversion efficiency as well as good CM noise insulation.

Yu. V. Obnosov - One of the best experts on this subject based on the ideXlab platform.