The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
George A Constantinides - One of the best experts on this subject based on the ideXlab platform.
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a parallel hardware architecture for scale and rotation invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel hardware architecture for image Feature Detection based on the scale invariant Feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect Features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy.
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a parallel hardware architecture for scale and rotation invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel hardware architecture for image Feature Detection based on the scale invariant Feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect Features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy.
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a parallel hardware architecture for image Feature Detection
Applied Reconfigurable Computing, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time parallel hardware architecture for image Feature Detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected Features, where each one is identified by their coordinates, scale and octave. In addition, the proposed hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the Feature descriptors. This work also presents a suitable parameter set for hardware implementation of the SIFT algorithm and proposes specific hardware optimizations considered fundamental to embed whole system on a single chip, which implements in parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of Features.
Vanderlei Bonato - One of the best experts on this subject based on the ideXlab platform.
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a parallel hardware architecture for scale and rotation invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel hardware architecture for image Feature Detection based on the scale invariant Feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect Features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy.
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a parallel hardware architecture for scale and rotation invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel hardware architecture for image Feature Detection based on the scale invariant Feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect Features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy.
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a parallel hardware architecture for image Feature Detection
Applied Reconfigurable Computing, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time parallel hardware architecture for image Feature Detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected Features, where each one is identified by their coordinates, scale and octave. In addition, the proposed hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the Feature descriptors. This work also presents a suitable parameter set for hardware implementation of the SIFT algorithm and proposes specific hardware optimizations considered fundamental to embed whole system on a single chip, which implements in parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of Features.
Kang G Shin - One of the best experts on this subject based on the ideXlab platform.
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in band spectrum sensing in cognitive radio networks energy Detection or Feature Detection
ACM IEEE International Conference on Mobile Computing and Networking, 2008Co-Authors: Hyoil Kim, Kang G ShinAbstract:In a cognitive radio network (CRN), in-band spectrum sensing is essential for the protection of legacy spectrum users, with which the presence of primary users (PUs) can be detected promptly, allowing secondary users (SUs) to vacate the channels immediately. For in-band sensing, it is important to meet the detectability requirements, such as the maximum allowed latency of Detection (e.g., 2 seconds in IEEE 802.22) and the probability of mis-Detection and false-alarm. In this paper, we propose an effcient periodic in-band sensing algorithm that optimizes sensing-frequency and sensing-time by minimizing sensing overhead while meeting the detectability requirements. The proposed scheme determines the better of energy or Feature Detection that incurs less sensing overhead at each SNR level, and derives the threshold aRSSthreshold on the average received signal strength (RSS) of a primary signal below which Feature Detection is preferred. We showed that energy Detection under lognormal shadowing could still perform well at the average SNR
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in band spectrum sensing in cognitive radio networks energy Detection or Feature Detection
ACM IEEE International Conference on Mobile Computing and Networking, 2008Co-Authors: Hyoil Kim, Kang G ShinAbstract:In a cognitive radio network (CRN), in-band spectrum sensing is essential for the protection of legacy spectrum users, with which the presence of primary users (PUs) can be detected promptly, allowing secondary users (SUs) to vacate the channels immediately. For in-band sensing, it is important to meet the detectability requirements, such as the maximum allowed latency of Detection (e.g., 2 seconds in IEEE 802.22) and the probability of mis-Detection and false-alarm. In this paper, we propose an effcient periodic in-band sensing algorithm that optimizes sensing-frequency and sensing-time by minimizing sensing overhead while meeting the detectability requirements. The proposed scheme determines the better of energy or Feature Detection that incurs less sensing overhead at each SNR level, and derives the threshold aRSSthreshold on the average received signal strength (RSS) of a primary signal below which Feature Detection is preferred. We showed that energy Detection under lognormal shadowing could still perform well at the average SNR < SNRwall [1] when collaborative sensing is used for its location diversity. Two key factors affecting Detection performance are also considered: noise uncertainty and inter-CRN interference. aRSSthreshold appears to lie between -114.6 dBm and -109.9 dBm with the noise uncertainty ranging from 0.5 dB to 2 dB, and between -112.9 dBm and -110.5 dBm with 1~6 interfering CRNs.
Eduardo Marques - One of the best experts on this subject based on the ideXlab platform.
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a parallel hardware architecture for scale and rotation invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel hardware architecture for image Feature Detection based on the scale invariant Feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect Features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy.
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a parallel hardware architecture for scale and rotation invariant Feature Detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel hardware architecture for image Feature Detection based on the scale invariant Feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect Features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy.
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a parallel hardware architecture for image Feature Detection
Applied Reconfigurable Computing, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time parallel hardware architecture for image Feature Detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected Features, where each one is identified by their coordinates, scale and octave. In addition, the proposed hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the Feature descriptors. This work also presents a suitable parameter set for hardware implementation of the SIFT algorithm and proposes specific hardware optimizations considered fundamental to embed whole system on a single chip, which implements in parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of Features.
Yexuan Qiu - One of the best experts on this subject based on the ideXlab platform.
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a hydrologic Feature Detection algorithm to quantify seasonal components of flow regimes
Journal of Hydrology, 2020Co-Authors: Noelle K Patterson, Belize A Lane, Samuel Sandovalsolis, Gregory B Pasternack, Sarah M Yarnell, Yexuan QiuAbstract:Abstract Seasonal flow transitions between wet and dry conditions are a primary control on river conditions, including biogeochemical processes and aquatic life-history strategies. In regions like California with highly seasonal flow patterns and immense interannual variability, a rigorous approach is needed to accurately identify and quantify seasonal flow transitions from the annual flow regime. Drawing on signal processing theory, this study develops a transferable approach to detect the timing of seasonal flow transitions from daily streamflow time series using an iterative smoothing, Feature Detection, and windowing methodology. The approach is shown to accurately identify and characterize seasonal flows across highly variable natural flow regimes in California. A quantitative error assessment validated the accuracy of the approach, finding that inaccuracies in seasonal timing identification did not exceed 10%, with infrequent exceptions. Results for seasonal timing were also used to highlight the statistically distinct timing found across streams with varying climatic drivers in California. The proposed approach improves understanding of spatial and temporal trends in hydrologic processes and climate conditions across complex landscapes and informs environmental water management efforts by delineating timing of seasonal flows.
