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Pooria M Yaghini - One of the best experts on this subject based on the ideXlab platform.

  • fault tolerance assessment of pic microcontroller based on fault injection
    2009 10th Latin American Test Workshop, 2009
    Co-Authors: Ashkan Eghbal, Hamid R Zarandi, Pooria M Yaghini
    Abstract:

    In this paper the fault tolerance behavior of a PIC micro-controller has been concerned by fault injection method. This experiment is based on injection of 70 different transient faults in various points. The faults have been injected into a structural-level VHDL model. Repeating each experiment for 200 times, result in 14000 transient fault injections into model of this microcontroller. The experimental results have been compared in different aspects. Up to 50% of the injected faults cause system failure and also about 50% are recovered before changing into errors. Less than 1% of injected faults treat as latent errors. Program counter is distinguished as the most infected components after simulated comparisons. The failure rate of this part is near to 90%. Moreover, the controller and File Register stand on the second and third status by the failure rates of 68% and 64%, respectively.

Ashkan Eghbal - One of the best experts on this subject based on the ideXlab platform.

  • fault tolerance assessment of pic microcontroller based on fault injection
    2009 10th Latin American Test Workshop, 2009
    Co-Authors: Ashkan Eghbal, Hamid R Zarandi, Pooria M Yaghini
    Abstract:

    In this paper the fault tolerance behavior of a PIC micro-controller has been concerned by fault injection method. This experiment is based on injection of 70 different transient faults in various points. The faults have been injected into a structural-level VHDL model. Repeating each experiment for 200 times, result in 14000 transient fault injections into model of this microcontroller. The experimental results have been compared in different aspects. Up to 50% of the injected faults cause system failure and also about 50% are recovered before changing into errors. Less than 1% of injected faults treat as latent errors. Program counter is distinguished as the most infected components after simulated comparisons. The failure rate of this part is near to 90%. Moreover, the controller and File Register stand on the second and third status by the failure rates of 68% and 64%, respectively.

Hamid R Zarandi - One of the best experts on this subject based on the ideXlab platform.

  • fault tolerance assessment of pic microcontroller based on fault injection
    2009 10th Latin American Test Workshop, 2009
    Co-Authors: Ashkan Eghbal, Hamid R Zarandi, Pooria M Yaghini
    Abstract:

    In this paper the fault tolerance behavior of a PIC micro-controller has been concerned by fault injection method. This experiment is based on injection of 70 different transient faults in various points. The faults have been injected into a structural-level VHDL model. Repeating each experiment for 200 times, result in 14000 transient fault injections into model of this microcontroller. The experimental results have been compared in different aspects. Up to 50% of the injected faults cause system failure and also about 50% are recovered before changing into errors. Less than 1% of injected faults treat as latent errors. Program counter is distinguished as the most infected components after simulated comparisons. The failure rate of this part is near to 90%. Moreover, the controller and File Register stand on the second and third status by the failure rates of 68% and 64%, respectively.

Erika Gunadi - One of the best experts on this subject based on the ideXlab platform.

  • Physical Register Inlining
    2004
    Co-Authors: Physical Register Inlining, Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi
    Abstract:

    Physical Register access time increases the delay between scheduling and execution in modern out-of-order processors. As the number of physical Registers increases, this delay grows, forcing designers to employ Register Files with multicycle access. This paper advocates more efficient utilization of a fewer number of physical Registers in order to reduce the access time of the physical Register File. Register values with few significant bits are stored in the rename map using physical Register inlining, a scheme analogous to inlining of operand fields in data structures. Specifically, whenever a Register value can be expressed with fewer bits than the Register map would need to specify a physical Register number, the value is stored directly in the map,avoiding the indirection, and saving space in the physical Register File. Not surprisingly, we find that a significant portion of all Register operands can be stored in the map in this fashion, and describe straightforward microarchitectural extensions that correctly implement physical Register inlining. We find that physical Register inlining performs well, particularly in processors that are Register-constrained

Physical Register Inlining - One of the best experts on this subject based on the ideXlab platform.

  • Physical Register Inlining
    2004
    Co-Authors: Physical Register Inlining, Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi
    Abstract:

    Physical Register access time increases the delay between scheduling and execution in modern out-of-order processors. As the number of physical Registers increases, this delay grows, forcing designers to employ Register Files with multicycle access. This paper advocates more efficient utilization of a fewer number of physical Registers in order to reduce the access time of the physical Register File. Register values with few significant bits are stored in the rename map using physical Register inlining, a scheme analogous to inlining of operand fields in data structures. Specifically, whenever a Register value can be expressed with fewer bits than the Register map would need to specify a physical Register number, the value is stored directly in the map,avoiding the indirection, and saving space in the physical Register File. Not surprisingly, we find that a significant portion of all Register operands can be stored in the map in this fashion, and describe straightforward microarchitectural extensions that correctly implement physical Register inlining. We find that physical Register inlining performs well, particularly in processors that are Register-constrained