The Experts below are selected from a list of 20451 Experts worldwide ranked by ideXlab platform
T. N. Vijaykumar - One of the best experts on this subject based on the ideXlab platform.
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opportunistic Transient Fault detection
IEEE Micro, 2006Co-Authors: Mohamed Gomaa, T. N. VijaykumarAbstract:CMOS scaling continues to enable faster transistors and lower supply voltage, improving microprocessor performance and reducing per-transistor power. The downside of scaling is increased susceptibility to soft errors due to strikes by cosmic particles and radiation from packaging materials. The result is degraded reliability in future commodity microprocessors. The authors target better coverage while incurring minimal performance degradation by opportunistically using redundancy
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opportunistic Transient Fault detection
International Symposium on Computer Architecture, 2005Co-Authors: Mohamed Gomaa, T. N. VijaykumarAbstract:CMOS scaling increases susceptibility of microprocessors to Transient Faults. Most current proposals for Transient-Fault detection use full redundancy to achieve perfect coverage while incurring significant performance degradation. However, most commodity systems do not need or provide perfect coverage. A recent paper explores this leniency to reduce the soft-error rate of the issue queue during L2 misses while incurring minimal performance degradation. Whereas the previous paper reduces soft-error rate without using any redundancy, we target better coverage while incurring similarly-minimal performance degradation by opportunistically using redundancy. We propose two semi-complementary techniques, called partial explicit redundancy (PER) and implicit redundancy through reuse (IRTR), to explore the trade-off between soft-error rate and performance. PER opportunistically exploits low-ILP phases and L2 misses to introduce explicit redundancy with minimal performance degradation. Because PER covers the entire pipeline and exploits not only L2 misses but all low-ILP phases, PER achieves better coverage than the previous work. To achieve coverage in high-ILP phases as well, we propose implicit redundancy through reuse (IRTR). Previous work exploits the phenomenon of instruction reuse to avoid redundant execution while falling back on redundant execution when there is no reuse. IRTR takes reuse to the extreme of performance-coverage trade-off and completely avoids explicit redundancy by exploiting reuseýs implicit redundancy within the main thread for Fault detection with virtually no performance degradation. Using simulations with SPEC2000, we show that PER and IRTR achieve better trade-off between soft-error rate and performance degradation than the previous schemes.
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Transient Fault recovery for chip multiprocessors
IEEE Micro, 2003Co-Authors: Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith PomeranzAbstract:Chip-level redundant threading with recovery (CRTR) for chip multiprocessors extends previous Transient-Fault detection schemes to provide Fault recovery. To hide interprocessor latency, CRTR uses a long slack enabled by asymmetric commit and uses the trailing thread state for recovery. CRTR increases bandwidth supply by pipelining communication paths and reduces bandwidth demand by extending the dependence-based checking elision.
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Transient Fault recovery for chip multiprocessors
International Symposium on Computer Architecture, 2003Co-Authors: Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith PomeranzAbstract:To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to Transient Faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR). CRTR extends the previously-proposed CRT for Transient-Fault detection in CMPs, and the previously-proposed SRTR for Transient-Fault recovery in SMT. All these schemes achieve Fault tolerance by executing and comparing two copies, called leading and trailing threads, of a given application. Previous recovery schemes for SMT do not perform well on CMPs. In a CMP, the leading and trailing threads execute on different processors to achieve load balancing and reduce the probability of a Fault corrupting both threads; whereas in an SMT, both threads execute on the same processor. The inter-processor communication required to compare the threads introduces latency and bandwidth problems not present in an SMT.To hide inter-processor latency, CRTR executes the leading thread ahead of the trailing thread by maintaining a long slack, enabled by asymmetric commit. CRTR commits the leading thread before checking and the trailing thread after checking, so that the trailing thread state may be used for recovery. Previous recovery schemes commit both threads after checking, making a long slack suboptimal. To tackle inter-processor bandwidth, CRTR not only increases the bandwidth supply by pipelining the communication paths, but also reduces the bandwidth demand. By reasoning that Faults propagate through dependences, previously-proposed Dependence-Based Checking Elision (DBCE) exploits (true) register dependence chains so that only the value of the last instruction in a chain is checked. However, instructions that mask operand bits may mask Faults and limit the use of dependence chains. We propose Death- and Dependence-Based Checking Elision (DDBCE), which chains a masking instruction only if the source operand of the instruction dies after the instruction. Register deaths ensure that masked Faults do not corrupt later computation. Using SPEC2000, we show that CRTR incurs negligible performance loss compared to CRT for inter-processor (one-way) latency as high as 30 cycles, and that the bandwidth requirements of CRT and CRTR with DDBCE are 5.2 and 7.1 bytes/cycle, respectively.
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Transient Fault recovery using simultaneous multithreading
International Symposium on Computer Architecture, 2002Co-Authors: T. N. Vijaykumar, Irith Pomeranz, Karl ChengAbstract:We propose a scheme for Transient-Fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for Transient-Fault detection, called Simultaneously and Redundantly Threaded (SRT) processors. SRT replicates an application into two communicating threads, one executing ahead of the other. The trailing thread repeats the computation performed by the leading thread, and the values produced by the two threads are compared. In SRT, a leading instruction may commit before the check for Faults occurs, relying on the trailing thread to trigger detection. In contrast, SRTR must not allow any leading instruction to commit before checking occurs, since a Faulty instruction cannot be undone once the instruction commits.To avoid stalling leading instructions at commit while waiting for their trailing counterparts, SRTR exploits the time between the completion and commit of leading instructions. SRTR compares the leading and trailing values as soon as the trailing instruction completes, typically before the leading instruction reaches the commit point. To avoid increasing the bandwidth demand on the register file for checking register values, SRTR uses the register value queue (RVQ) to hold register values for checking. To reduce the bandwidth pressure on the RVQ itself, SRTR employs dependence-based checking elision (DBCE). By reasoning that Faults propagate through dependent instructions, DBCE exploits register (true) dependence chains so that only the last instruction in a chain uses the RVQ, and has the leading and trailing values checked. SRTR performs within 1% and 7% of SRT for SPEC95 integer and floating-point programs, respectively: While SRTR without DBCE incurs about 18% performance loss when the number of RVQ ports is reduced from four (which is performance-equivalent to an unlimited number) to two ports, with DBCE, a two-ported RVQ performs within 2% of a four-ported RVQ.
Mohamed Gomaa - One of the best experts on this subject based on the ideXlab platform.
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opportunistic Transient Fault detection
IEEE Micro, 2006Co-Authors: Mohamed Gomaa, T. N. VijaykumarAbstract:CMOS scaling continues to enable faster transistors and lower supply voltage, improving microprocessor performance and reducing per-transistor power. The downside of scaling is increased susceptibility to soft errors due to strikes by cosmic particles and radiation from packaging materials. The result is degraded reliability in future commodity microprocessors. The authors target better coverage while incurring minimal performance degradation by opportunistically using redundancy
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opportunistic Transient Fault detection
International Symposium on Computer Architecture, 2005Co-Authors: Mohamed Gomaa, T. N. VijaykumarAbstract:CMOS scaling increases susceptibility of microprocessors to Transient Faults. Most current proposals for Transient-Fault detection use full redundancy to achieve perfect coverage while incurring significant performance degradation. However, most commodity systems do not need or provide perfect coverage. A recent paper explores this leniency to reduce the soft-error rate of the issue queue during L2 misses while incurring minimal performance degradation. Whereas the previous paper reduces soft-error rate without using any redundancy, we target better coverage while incurring similarly-minimal performance degradation by opportunistically using redundancy. We propose two semi-complementary techniques, called partial explicit redundancy (PER) and implicit redundancy through reuse (IRTR), to explore the trade-off between soft-error rate and performance. PER opportunistically exploits low-ILP phases and L2 misses to introduce explicit redundancy with minimal performance degradation. Because PER covers the entire pipeline and exploits not only L2 misses but all low-ILP phases, PER achieves better coverage than the previous work. To achieve coverage in high-ILP phases as well, we propose implicit redundancy through reuse (IRTR). Previous work exploits the phenomenon of instruction reuse to avoid redundant execution while falling back on redundant execution when there is no reuse. IRTR takes reuse to the extreme of performance-coverage trade-off and completely avoids explicit redundancy by exploiting reuseýs implicit redundancy within the main thread for Fault detection with virtually no performance degradation. Using simulations with SPEC2000, we show that PER and IRTR achieve better trade-off between soft-error rate and performance degradation than the previous schemes.
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Transient Fault recovery for chip multiprocessors
IEEE Micro, 2003Co-Authors: Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith PomeranzAbstract:Chip-level redundant threading with recovery (CRTR) for chip multiprocessors extends previous Transient-Fault detection schemes to provide Fault recovery. To hide interprocessor latency, CRTR uses a long slack enabled by asymmetric commit and uses the trailing thread state for recovery. CRTR increases bandwidth supply by pipelining communication paths and reduces bandwidth demand by extending the dependence-based checking elision.
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Transient Fault recovery for chip multiprocessors
International Symposium on Computer Architecture, 2003Co-Authors: Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith PomeranzAbstract:To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to Transient Faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR). CRTR extends the previously-proposed CRT for Transient-Fault detection in CMPs, and the previously-proposed SRTR for Transient-Fault recovery in SMT. All these schemes achieve Fault tolerance by executing and comparing two copies, called leading and trailing threads, of a given application. Previous recovery schemes for SMT do not perform well on CMPs. In a CMP, the leading and trailing threads execute on different processors to achieve load balancing and reduce the probability of a Fault corrupting both threads; whereas in an SMT, both threads execute on the same processor. The inter-processor communication required to compare the threads introduces latency and bandwidth problems not present in an SMT.To hide inter-processor latency, CRTR executes the leading thread ahead of the trailing thread by maintaining a long slack, enabled by asymmetric commit. CRTR commits the leading thread before checking and the trailing thread after checking, so that the trailing thread state may be used for recovery. Previous recovery schemes commit both threads after checking, making a long slack suboptimal. To tackle inter-processor bandwidth, CRTR not only increases the bandwidth supply by pipelining the communication paths, but also reduces the bandwidth demand. By reasoning that Faults propagate through dependences, previously-proposed Dependence-Based Checking Elision (DBCE) exploits (true) register dependence chains so that only the value of the last instruction in a chain is checked. However, instructions that mask operand bits may mask Faults and limit the use of dependence chains. We propose Death- and Dependence-Based Checking Elision (DDBCE), which chains a masking instruction only if the source operand of the instruction dies after the instruction. Register deaths ensure that masked Faults do not corrupt later computation. Using SPEC2000, we show that CRTR incurs negligible performance loss compared to CRT for inter-processor (one-way) latency as high as 30 cycles, and that the bandwidth requirements of CRT and CRTR with DDBCE are 5.2 and 7.1 bytes/cycle, respectively.
Anirban Sengupta - One of the best experts on this subject based on the ideXlab platform.
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spatial and temporal redundancy for Transient Fault tolerant datapath
IEEE Transactions on Aerospace and Electronic Systems, 2018Co-Authors: Anirban Sengupta, Deepak KachaveAbstract:In application specific integrated circuits used in aircraft control systems the effects of Transient Fault, both in temporal and spatial domain emanating from a single particle strike, cannot be ignored anymore. This is due to scaling of device geometry and surge in frequency. This paper presents novel Fault-tolerant high-level synthesis methodology against temporal and spatial impacts of Transient at reduced design cost (avg. ∼ 25%) and power (avg. ∼ 48%) than a recent approach.
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low cost Fault tolerance against kc cycle and km unit Transient for loop based control data flow graphs during physically aware high level synthesis
Microelectronics Reliability, 2017Co-Authors: Anirban Sengupta, Deepak KachaveAbstract:Abstract Recent literatures have proved that current technologies pose grave reliability concern for digital devices due to possibility of multiple (k m )-unit Transient Fault (MTF) and multi (k c )-cycle Transient Fault (MCT) emanating from particle strike with moderate linear energy transfer (LET). This has arisen due to massive scaling in device dimensions and surge in device frequency happening so far. In the literature solutions for Fault tolerant design, that can address MTF and MCT simultaneously during high level synthesis (HLS) for both loop based and non-loop based applications, does not exist. This paper presents the following novel contributions: (a) novel Fault tolerant HLS methodology for simultaneously providing multi-cycle (control step) and multi-unit Transient Fault tolerance for loop based control data flow graphs (b) novel HLS methodology for low cost design solution through exploration of Fault tolerant hardware configuration and loop unrolling factor. Results of the proposed approach on standard benchmarks yielded Fault tolerant solutions with significantly reduced design cost (average ~ 27%) and power consumption (average ~ 61%) when compared to a recent similar approach.
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swarm intelligence driven design space exploration of optimal k cycle Transient Fault secured datapath during high level synthesis based on user power delay budget
Microelectronics Reliability, 2015Co-Authors: Anirban Sengupta, Reza SedaghatAbstract:Abstract Fault security indicates ability to provide error detection or fetch correct output. Fault security assures possibility of using either hardware redundancy or time redundancy to optimize the overheads associated with Fault security. However, generation (design space exploration (DSE)) of an optimal Fault secured datapath structure based on user power–delay budget during high level synthesis (HLS) in the context k-cycle Transient Fault is considered an intractable problem. This is due to the fact that for every type of candidate design solution produced during exploration, a feasible k-cycle Fault secured datapath may not exist which satisfies the conflicting user constraints/budget. Secondly, insertion of inapt cut (resulting in an additional checkpoint) to optimize delay overhead associated with Fault security in most cases may not result in optimal solutions in the context of user constraints/budgets. The solutions to the above problems have not been addressed in the literature so far. The paper therefore presents the following novelties: (a) an algorithm for Fault secured DSE process (b) handling k-cycle Transient Faults during DSE (c) schemes for selecting appropriate edges for inserting cuts that selects available locations in the scheduled Control Data Flow Graph (CDFG) which minimizes delay overhead associated with Fault security (d) swarm intelligence (particle swarm optimization) driven DSE process that adaptively/intelligently computes the candidate design solutions for generating an optimal Fault secured datapath. Results of the proposed approach when tested on standard benchmarks yielded optimal results in most cases as evident from the data obtained for generational distance (GD), spacing (S), spreading (Δ) and weighted metric (Wm). Further, results of comparison with a recent approaches indicated significant reduction of final cost (better quality) for the proposed approach.
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automated design space exploration of multi cycle Transient Fault detectable datapath based on multi objective user constraints for application specific computing
Advances in Engineering Software, 2015Co-Authors: Anirban Sengupta, Saumya BhadauriaAbstract:Novel exploration approach for multi-cycle Transient Fault detectable datapath.Novel mechanism for detecting multi-cycle Transient Fault.Performs tradeoff between power and execution delay.Provides an average improvement in QoR of >9% compared to 15. A novel automated design space exploration (DSE) approach of multi-cycle Transient Fault detectable datapath based on multi-objective user constraints (power and delay) for application specific computing is presented in this paper. To the best of the authors' knowledge, this is the first work in the literature to solve this problem. The presented approach, driven by bacterial foraging optimization (BFO) algorithm provides easy flexibility to change direction in the design space through tumble/swim actions if a search path is found ineffective. The approach is highly capable of reaching true Pareto optimal curve indicated by the closeness of our non-dominated solutions to the true Pareto front and their uniform distribution over the Pareto curve (implying diversity). The contributions of this paper are as follows: (a) novel exploration approach for generating a high quality Fault detectable structure based on user provided requirements of power-delay, which is capable of Transient error detection in the datapath; (b) novel Fault detectable algorithm for handling single and multi-cycle Transient Faults.The results of the proposed approach indicated an average improvement in Quality of Results (QoR) of >9% and reduction in hardware usage of >23% compared to recent approaches that are closer in solving a similar objective.
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user power delay budget driven pso based design space exploration of optimal k cycle Transient Fault secured datapath during high level synthesis
International Symposium on Quality Electronic Design, 2015Co-Authors: Anirban Sengupta, Saumya BhadauriaAbstract:Fault security indicates ability to provide error detection or fetching the correct output. Generation (design space exploration (DSE)) of an optimal Fault secured datapath structure based on user power-delay budget during high level synthesis (HLS) in the context k-cycle Transient Fault is considered an intractable problem. This is due to the fact that for every type of candidate design solution produced during exploration, a feasible k-cycle Fault secured datapath may not exist satisfying the conflicting user constraints/budget. Secondly, insertion of random cut to optimize delay overhead associated with Fault security in most cases may not yield optimal solutions in the context of user constraints/budgets. The solutions to the above problems have not been addressed in the literature so far. The paper solves the problem by presenting: (a) a novel algorithm for Fault secured particle swarm optimization driven DSE (b) novel technique for handling k-cycle Transient Faults (c) novel schemes for selecting appropriate edges for inserting cuts in the scheduled Control Data Flow Graph (CDFG) minimizing delay overhead associated with Fault security. The proposed approach yielded optimal results which minimizes hybrid cost as well as satisfies user constraints. Further, results of comparison with recent approaches indicated significant reduction of final cost.
Xiuchen Jiang - One of the best experts on this subject based on the ideXlab platform.
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a novel Transient Fault current sensor based on the pcb rogowski coil for overhead transmission lines
Sensors, 2016Co-Authors: Yadong Liu, Xiaolei Xie, Yong Qian, Gehao Sheng, Xiuchen JiangAbstract:The accurate detection of high-frequency Transient Fault currents in overhead transmission lines is the basis of malfunction detection and diagnosis. This paper proposes a novel differential winding printed circuit board (PCB) Rogowski coil for the detection of Transient Fault currents in overhead transmission lines. The interference mechanism of the sensor surrounding the overhead transmission line is analyzed and the guideline for the interference elimination is obtained, and then a differential winding printed circuit board (PCB) Rogowski coil is proposed, where the branch and return line of the PCB coil were designed to be strictly symmetrical by using a joining structure of two semi-rings and collinear twisted pair differential windings in each semi-ring. A serial test is conducted, including the frequency response, linearity, and anti-interference performance as well as a comparison with commercial sensors. Results show that a PCB Rogowski coil has good linearity and resistance to various external magnetic field interferences, thus enabling it to be widely applied in Fault-current-collecting devices.
Irith Pomeranz - One of the best experts on this subject based on the ideXlab platform.
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Transient Fault recovery for chip multiprocessors
IEEE Micro, 2003Co-Authors: Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith PomeranzAbstract:Chip-level redundant threading with recovery (CRTR) for chip multiprocessors extends previous Transient-Fault detection schemes to provide Fault recovery. To hide interprocessor latency, CRTR uses a long slack enabled by asymmetric commit and uses the trailing thread state for recovery. CRTR increases bandwidth supply by pipelining communication paths and reduces bandwidth demand by extending the dependence-based checking elision.
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Transient Fault recovery for chip multiprocessors
International Symposium on Computer Architecture, 2003Co-Authors: Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith PomeranzAbstract:To address the increasing susceptibility of commodity chip multiprocessors (CMPs) to Transient Faults, we propose Chiplevel Redundantly Threaded multiprocessor with Recovery (CRTR). CRTR extends the previously-proposed CRT for Transient-Fault detection in CMPs, and the previously-proposed SRTR for Transient-Fault recovery in SMT. All these schemes achieve Fault tolerance by executing and comparing two copies, called leading and trailing threads, of a given application. Previous recovery schemes for SMT do not perform well on CMPs. In a CMP, the leading and trailing threads execute on different processors to achieve load balancing and reduce the probability of a Fault corrupting both threads; whereas in an SMT, both threads execute on the same processor. The inter-processor communication required to compare the threads introduces latency and bandwidth problems not present in an SMT.To hide inter-processor latency, CRTR executes the leading thread ahead of the trailing thread by maintaining a long slack, enabled by asymmetric commit. CRTR commits the leading thread before checking and the trailing thread after checking, so that the trailing thread state may be used for recovery. Previous recovery schemes commit both threads after checking, making a long slack suboptimal. To tackle inter-processor bandwidth, CRTR not only increases the bandwidth supply by pipelining the communication paths, but also reduces the bandwidth demand. By reasoning that Faults propagate through dependences, previously-proposed Dependence-Based Checking Elision (DBCE) exploits (true) register dependence chains so that only the value of the last instruction in a chain is checked. However, instructions that mask operand bits may mask Faults and limit the use of dependence chains. We propose Death- and Dependence-Based Checking Elision (DDBCE), which chains a masking instruction only if the source operand of the instruction dies after the instruction. Register deaths ensure that masked Faults do not corrupt later computation. Using SPEC2000, we show that CRTR incurs negligible performance loss compared to CRT for inter-processor (one-way) latency as high as 30 cycles, and that the bandwidth requirements of CRT and CRTR with DDBCE are 5.2 and 7.1 bytes/cycle, respectively.
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Transient Fault recovery using simultaneous multithreading
International Symposium on Computer Architecture, 2002Co-Authors: T. N. Vijaykumar, Irith Pomeranz, Karl ChengAbstract:We propose a scheme for Transient-Fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for Transient-Fault detection, called Simultaneously and Redundantly Threaded (SRT) processors. SRT replicates an application into two communicating threads, one executing ahead of the other. The trailing thread repeats the computation performed by the leading thread, and the values produced by the two threads are compared. In SRT, a leading instruction may commit before the check for Faults occurs, relying on the trailing thread to trigger detection. In contrast, SRTR must not allow any leading instruction to commit before checking occurs, since a Faulty instruction cannot be undone once the instruction commits.To avoid stalling leading instructions at commit while waiting for their trailing counterparts, SRTR exploits the time between the completion and commit of leading instructions. SRTR compares the leading and trailing values as soon as the trailing instruction completes, typically before the leading instruction reaches the commit point. To avoid increasing the bandwidth demand on the register file for checking register values, SRTR uses the register value queue (RVQ) to hold register values for checking. To reduce the bandwidth pressure on the RVQ itself, SRTR employs dependence-based checking elision (DBCE). By reasoning that Faults propagate through dependent instructions, DBCE exploits register (true) dependence chains so that only the last instruction in a chain uses the RVQ, and has the leading and trailing values checked. SRTR performs within 1% and 7% of SRT for SPEC95 integer and floating-point programs, respectively: While SRTR without DBCE incurs about 18% performance loss when the number of RVQ ports is reduced from four (which is performance-equivalent to an unlimited number) to two ports, with DBCE, a two-ported RVQ performs within 2% of a four-ported RVQ.