The Experts below are selected from a list of 261 Experts worldwide ranked by ideXlab platform
A P Vinod - One of the best experts on this subject based on the ideXlab platform.
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a new common subexpression elimination algorithm for realizing low complexity higher order digital Filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: R Mahesh, A P VinodAbstract:The complexity of linear-phase finite-impulse-response (FIR) Filters is dominated by the complexity of Coefficient multipliers. The number of adders (subtractors) used to implement the multipliers determines the complexity of the FIR Filters. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) Coefficients reduce the number of adders required in the multipliers of FIR Filters. A new CSE algorithm using binary representation of Coefficients for the implementation of higher order FIR Filters with a fewer number of adders than CSD-based CSE methods is presented in this paper. We show that the CSE method is more efficient in reducing the number of adders needed to realize the multipliers when the Filter Coefficients are represented in the binary form. Our observation is that the number of unpaired bits (bits that do not form CSs) is considerably few for binary Coefficients compared to CSD Coefficients, particularly for higher order FIR Filters. As a result, the proposed binary-Coefficient-based CSE method offers good reduction in the number of adders in realizing higher order Filters. The reduction of adders is achieved without much increase in critical path length of Filter Coefficient multipliers. Design examples of FIR Filters show that our method offers an average adder reduction of 18% over the best known CSE method, without any increase in the logic depth.
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A new common subexpression elimination algorithm for implementing low complexity FIR Filters in software defined radio receivers
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: R Mahesh, A P VinodAbstract:The complexity of linear phase finite impulse response (FIR) Filters used in the channelizer of a software defined radio (SDR) receiver is dominated by the complexity of Coefficient multipliers. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) Coefficients produce low complexity FIR Filter Coefficient multipliers. A new CSE algorithm based on the binary representation of Filter Coefficients is presented in the paper. Design examples of channel Filters employed in the digital advanced mobile phone systems (D-AMPS) and personal digital cellular (PDC) receivers show that the proposed method offers an average adder reduction of 23% over the conventional CSD-based CSE method
R Mahesh - One of the best experts on this subject based on the ideXlab platform.
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a new common subexpression elimination algorithm for realizing low complexity higher order digital Filters
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: R Mahesh, A P VinodAbstract:The complexity of linear-phase finite-impulse-response (FIR) Filters is dominated by the complexity of Coefficient multipliers. The number of adders (subtractors) used to implement the multipliers determines the complexity of the FIR Filters. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) Coefficients reduce the number of adders required in the multipliers of FIR Filters. A new CSE algorithm using binary representation of Coefficients for the implementation of higher order FIR Filters with a fewer number of adders than CSD-based CSE methods is presented in this paper. We show that the CSE method is more efficient in reducing the number of adders needed to realize the multipliers when the Filter Coefficients are represented in the binary form. Our observation is that the number of unpaired bits (bits that do not form CSs) is considerably few for binary Coefficients compared to CSD Coefficients, particularly for higher order FIR Filters. As a result, the proposed binary-Coefficient-based CSE method offers good reduction in the number of adders in realizing higher order Filters. The reduction of adders is achieved without much increase in critical path length of Filter Coefficient multipliers. Design examples of FIR Filters show that our method offers an average adder reduction of 18% over the best known CSE method, without any increase in the logic depth.
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A new common subexpression elimination algorithm for implementing low complexity FIR Filters in software defined radio receivers
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: R Mahesh, A P VinodAbstract:The complexity of linear phase finite impulse response (FIR) Filters used in the channelizer of a software defined radio (SDR) receiver is dominated by the complexity of Coefficient multipliers. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) Coefficients produce low complexity FIR Filter Coefficient multipliers. A new CSE algorithm based on the binary representation of Filter Coefficients is presented in the paper. Design examples of channel Filters employed in the digital advanced mobile phone systems (D-AMPS) and personal digital cellular (PDC) receivers show that the proposed method offers an average adder reduction of 23% over the conventional CSD-based CSE method
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Reconfigurable Low Complexity Fir Filters for Software Radio Receivers
2006 IEEE 17th International Symposium on Personal Indoor and Mobile Radio Communications, 2006Co-Authors: R Mahesh, Achutavarrier Prasad VinodAbstract:The most computationally demanding block of a software defined radio (SDR) receiver is the channelizer which operates at the highest sampling rate. Reconfigurability and low complexity are the two key requirements of the SDR channelizers. Two new reconfigurable architectures of low complexity finite impulse response (FIR) Filters for channelizers are proposed in this paper. Our methods are based on the binary common subexpression elimination (BCSE) algorithm. The proposed architectures are capable of operating at a high speed clock frequency of 109.7 MHz based on Xilinx's Virtex II 2v2000ff896-6 FPGA for a 12-bit FIR Filter Coefficient. Design examples show that our method offers an average reduction of 23% in the number of addition operations compared to the conventional FIR Filter implementations
Hao Wang - One of the best experts on this subject based on the ideXlab platform.
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a new separable two dimensional finite impulse response Filter design with sparse Coefficients
IEEE Transactions on Circuits and Systems, 2015Co-Authors: Hao WangAbstract:The separable two-dimensional (2-D) finite impulse response (FIR) Filter can be utilized to decrease the implementation complexity of the traditional 2-D FIR Filter. A novel separable 2-D FIR Filter design is proposed in this paper. The proposed design deals with a submatrix of the prototype 2-D FIR Filter Coefficient matrix, which contains all the information of the Filter Coefficient matrix. And, its basic idea is to try to utilize some column vectors of the submatrix itself to decompose this submatrix. There are zero-valued and/or one-valued Coefficients in the proposed Filter. In the Filter implementation, these zero-valued Coefficients do not require multipliers or adders. And, these one-valued Coefficients do not require multipliers. Additionally, an optimal design of the general separable 2-D FIR Filter in the mini-max sense and the least-square sense in the frequency domain is provided in a uniform framework, for the first time. Finally, the experimental comparison of the proposed separable 2-D FIR Filter design with other separable 2-D FIR Filter designs, and the comparison with other non-separable-structure low-complexity 2-D FIR Filter designs are provided to validate the superiority of the proposed method.
P K Meher - One of the best experts on this subject based on the ideXlab platform.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-I: REGULAR PAPERS 1 New Approach to Look-up-Table Design and Memory-Based Realization of FIR Digital Filter
2016Co-Authors: P K Meher, Senior MemberAbstract:Abstract—Distributed arithmetic (DA)-based computation is popular for its potential for efficient memory-based implementa-tion of finite impulse response (FIR) Filter where the Filter outputs are computed as inner-product of input-sample vectors and Filter-Coefficient vector. In this paper, however, we show that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the Filter Coefficients could be an area-efficient alternative to DA-based design of FIR Filter with the same throughput of implementation. By operand and inner-product decompositions, respectively, we have designed the conventional LUT-multiplier-based and DA-based structures for FIR Filter of equivalent throughput, where the LUT-multiplier-based design involves nearly the same mem-ory and the same number of adders, and less number of input register at the cost of slightly higher adder-widths than the other. Moreover, we present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. Besides, we present a modified transposed form FIR Filter, where a single segmented memory-core with only one pair of decoders are used to minimize the combinational area. The proposed LUT-based FIR Filter is found to involve nearly half the memory-space and (1/N) times the complexity of decoders and input-registers, at the cost of marginal increase in the width of the adders, and additional ∼ (4N×W) AND-OR-INVERT gates and ∼ (2N×W) NOR gates. We have synthesized the DA-based design and LUT-multiplier based design of 16-tap FIR Filters by Synopsys Design Compiler using TSMC 90 nm library, and find that the proposed LUT-multiplier-based design involves nearly 15 % less area than the DA-based design for the same throughput and lower latency of implementation. Index Terms—Memory-based computing, distributed arith-metic, FIR Filter, LUT-based computing, digital signal processing (DSP) chip, VLSI. I
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new approach to look up table design and memory based realization of fir digital Filter
IEEE Transactions on Circuits and Systems I-regular Papers, 2010Co-Authors: P K MeherAbstract:Distributed arithmetic (DA)-based computation is popular for its potential for efficient memory-based implementation of finite impulse response (FIR) Filter where the Filter outputs are computed as inner-product of input-sample vectors and Filter-Coefficient vector. In this paper, however, we show that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the Filter Coefficients could be an area-efficient alternative to DA-based design of FIR Filter with the same throughput of implementation. By operand and inner-product decompositions, respectively, we have designed the conventional LUT-multiplier-based and DA-based structures for FIR Filter of equivalent throughput, where the LUT-multiplier-based design involves nearly the same memory and the same number of adders, and less number of input register at the cost of slightly higher adder-widths than the other. Moreover, we present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. Besides, we present a modified transposed form FIR Filter, where a single segmented memory-core with only one pair of decoders are used to minimize the combinational area. The proposed LUT-based FIR Filter is found to involve nearly half the memory-space and $(1/N)$ times the complexity of decoders and input-registers, at the cost of marginal increase in the width of the adders, and additional $\sim(4N\times W)$ AND-OR-INVERT gates and $\sim(2N\times W)$ NOR gates. We have synthesized the DA-based design and LUT-multiplier based design of 16-tap FIR Filters by Synopsys Design Compiler using TSMC 90 nm library, and find that the proposed LUT-multiplier-based design involves nearly 15% less area than the DA-based design for the same throughput and lower latency of implementation.
Xianggui Guo - One of the best experts on this subject based on the ideXlab platform.
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h Filter design for delta operator formulated systems with low sensitivity to Filter Coefficient variations
Iet Control Theory and Applications, 2011Co-Authors: Xianggui Guo, Guanghong YangAbstract:The problem of designing H∞ Filters for delta operator formulated systems with low sensitivity to Filter Coefficient variations is investigated. The delta operator provides a theoretically unified formulation of continuous-time and discrete-time systems and also has the advantage of better numerical properties at high sampling rates. In addition to the standard H∞ criterion, the H∞ norm of the sensitivity function is introduced in order to improve the designed Filter's insensitivity to the Filter Coefficient variations. Finsler's Lemma is used to derive novel sufficient conditions which are adapted to treat this multiplicative objective optimisation problem in a potentially less conservative framework. Linear matrix inequality conditions are obtained for the existence of admissible Filters with respect to additive/multiplicative Coefficient variations based on two different types of sensitivity measures. Finally, the effectiveness of the proposed method is illustrated by a numerical example. It is shown that the delta operator approach offers better Coefficient sensitivity than the traditional shift operator approach when the sampling rate is high.
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brief paper insensitive h Filter design for continuous time systems with respect to Filter Coefficient variations
Automatica, 2010Co-Authors: Xianggui Guo, Guanghong YangAbstract:This paper is concerned with the problem of designing insensitive H"~ Filters for linear continuous-time systems. Coefficient sensitivity functions of transfer functions with respect to Filter additive/multiplicative Coefficient variations are defined, and the H"~ norms of the sensitivity functions are used to measure the sensitivity of the transfer functions with respect to additive Filter Coefficient variations. In addition, in order to deal with the Filter design problem for the multiplicative Filter Coefficient variation case, new measures based on the average of the sensitivity functions are also defined. Consequently, the insensitive H"~ Filter design problem is reduced to a multi-objective Filter design problem, which minimizes the Coefficient's sensitivity and meets the prescribed H"~ norm constraint simultaneously. First, a novel method for designing insensitive H"~ Filters subjected to additive Filter Coefficient variations is given in terms of the linear matrix inequality (LMI) optimization techniques. Furthermore, based on the new sensitivity measures, the obtained results are extended to the multiplicative Coefficient variation case. In addition, an indirect method for solving the multiplicative variations is also proposed. Finally, two numerical examples are provided to demonstrate the effectiveness of the proposed method.