The Experts below are selected from a list of 18489 Experts worldwide ranked by ideXlab platform
Bram Nauta - One of the best experts on this subject based on the ideXlab platform.
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Software Defined Radio receivers exploiting noise cancelling a tutorial review
IEEE Communications Magazine, 2014Co-Authors: Eric A. M. Klumperink, Bram NautaAbstract:Traditional Radio receivers were narrowband and dedicated to a single frequency band exploiting LC tanks, whereas Software Defined Radios target a flexibly programmable frequency. The broadband noise cancelling circuit technique has proven useful to achieve this target, as it breaks the traditional trade-off between low noise and broadband impedance matching. Different variants exist, with noise cancellation in the voltage or current domain, either at RF or after frequency translation to baseband. This article reviews the development of the noise cancelling technique and its role in inductorless interference robust Software Defined Radio receivers.
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on the suitability of discrete time receivers for Software Defined Radio
International Symposium on Circuits and Systems, 2007Co-Authors: Zhiyu Ru, Eric A. M. Klumperink, Bram NautaAbstract:CMOS Radio receiver architectures, based on Radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been proposed for dedicated Radio standards. This paper explores the suitability of such D-T receivers for highly flexible Software-Defined Radio (SDR) receivers. Via symbolic analysis and simulations the authors analyze the properties of D-T receivers, and show that at least three challenges exist to make a D-T receiver work for SDR: 1) the sampling clock frequency is related to the Radio frequency, complicating baseband filter design; 2) a frequency-dependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Compared to a mixer based Radio receiver, extra costs are needed to solve these problems.
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a polyphase multipath technique for Software Defined Radio transmitters
IEEE Journal of Solid-state Circuits, 2006Co-Authors: Rameswor Shrestha, Eric A. M. Klumperink, E Mensink, Gerard J M Wienk, Bram NautaAbstract:Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-mum CMOS, aiming at a Software-Defined Radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Omega load (2.54 Vpp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixers
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a polyphase multipath technique for Software Defined Radio transmitters
International Solid-State Circuits Conference, 2006Co-Authors: Rameswor Shrestha, Eric A. M. Klumperink, E Mensink, Gerard J M Wienk, Bram NautaAbstract:Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-μm CMOS, aiming at a Software-Defined Radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Ω load (2.54 V pp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixers.
Eric A. M. Klumperink - One of the best experts on this subject based on the ideXlab platform.
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Software Defined Radio receivers exploiting noise cancelling a tutorial review
IEEE Communications Magazine, 2014Co-Authors: Eric A. M. Klumperink, Bram NautaAbstract:Traditional Radio receivers were narrowband and dedicated to a single frequency band exploiting LC tanks, whereas Software Defined Radios target a flexibly programmable frequency. The broadband noise cancelling circuit technique has proven useful to achieve this target, as it breaks the traditional trade-off between low noise and broadband impedance matching. Different variants exist, with noise cancellation in the voltage or current domain, either at RF or after frequency translation to baseband. This article reviews the development of the noise cancelling technique and its role in inductorless interference robust Software Defined Radio receivers.
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on the suitability of discrete time receivers for Software Defined Radio
International Symposium on Circuits and Systems, 2007Co-Authors: Zhiyu Ru, Eric A. M. Klumperink, Bram NautaAbstract:CMOS Radio receiver architectures, based on Radio frequency (RF) sampling followed by discrete-time (D-T) signal processing via switched-capacitor circuits, have recently been proposed for dedicated Radio standards. This paper explores the suitability of such D-T receivers for highly flexible Software-Defined Radio (SDR) receivers. Via symbolic analysis and simulations the authors analyze the properties of D-T receivers, and show that at least three challenges exist to make a D-T receiver work for SDR: 1) the sampling clock frequency is related to the Radio frequency, complicating baseband filter design; 2) a frequency-dependent phase shift is introduced by pseudo-quadrature and pseudo-differential sampling; 3) the conversion gain of a charge sampling front-end is strongly frequency-dependent. Compared to a mixer based Radio receiver, extra costs are needed to solve these problems.
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a polyphase multipath technique for Software Defined Radio transmitters
IEEE Journal of Solid-state Circuits, 2006Co-Authors: Rameswor Shrestha, Eric A. M. Klumperink, E Mensink, Gerard J M Wienk, Bram NautaAbstract:Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-mum CMOS, aiming at a Software-Defined Radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Omega load (2.54 Vpp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixers
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a polyphase multipath technique for Software Defined Radio transmitters
International Solid-State Circuits Conference, 2006Co-Authors: Rameswor Shrestha, Eric A. M. Klumperink, E Mensink, Gerard J M Wienk, Bram NautaAbstract:Transmitter circuits using large signal swings and hard-switched mixers are power-efficient, but also produce unwanted harmonics and sidebands, which are commonly removed using dedicated filters. This paper presents a polyphase multipath technique to relax or eliminate filters by canceling a multitude of harmonics and sidebands. Using this technique, a wideband and flexible power upconverter with a clean output spectrum is realized in 0.13-μm CMOS, aiming at a Software-Defined Radio application. Prototype chips operate from DC to 2.4 GHz with spurs smaller than -40 dBc up to the 17th harmonic (18-path mode) or 5th harmonic (6-path mode) of the transmit frequency, without tuning or calibration. The transmitter delivers 8 mW of power to a 100-Ω load (2.54 V pp-diff voltage swing) and the complete chip consumes 228 mW from a 1.2-V supply. It uses no filters, but only digital circuits and mixers.
Sanjay Jinturkar - One of the best experts on this subject based on the ideXlab platform.
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A low-power multithreaded processor for Software Defined Radio
Journal of VLSI Signal Processing Systems for Signal Image and Video Technology, 2006Co-Authors: Michael Schulte, Suman Mamidi, John Glossner, Mayan Moudgill, Sanjay Jinturkar, Stamatis VassiliadisAbstract:Embedded digital signal processors for Software Defined Radio have stringent design constraints including high computational bandwidth, low power consumption, and low interrupt latency. Furthermore, due to rapidly evolving communication standards with increasing code complexity, these processors must be compiler-friendly, so that code for them can quickly be developed in a high-level language. In this paper, we present the design of the Sandblaster Processor, a low-power multithreaded digital signal processor for Software Defined Radio. The processor uses a unique combination of token triggered threading, powerful compound instructions, and SIMD vector operations to provide real-time baseband processing capabilities with very low power consumption. We describe the processor’s architecture and microarchitecture, along with various techniques for achieving high performance and low power dissipation. We also describe the processor’s programming environment and the SB3010 platform, a complete system-on-chip solution for Software Defined Radio. Using a super-computer class vectorizing compiler, the SB3010 achieves real-time performance in Software on a variety of communication protocols including 802.11b, GPS, AM/FM Radio, Bluetooth, GPRS, and WCDMA. In addition to providing a programmable platform for SDR, the processor also provides efficient support for a wide variety of digital signal processing and multimedia applications.
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Instruction set extensions for Software Defined Radio on a multithreaded processor
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Suman Mamidi, Emily R. Blem, John Glossner, Mayan Moudgill, Andrei Iancu, Daniela Iancu, Michael J. Schulte, Sanjay JinturkarAbstract:Software Defined Radios, which provide a programmable solution for implementing the physical layer processing of multiple communication standards, are widely recognized as one of the most important new technologies for wireless communication systems. Emerging communication standards, however, require tremendous processing capabilities to perform high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance benefits of these extensions are evaluated using a supercomputer class vectorizing compiler and the Sandblaster low-power multithreaded processor for Software Defined Radio. The proposed instruction set extensions provide significant performance improvements, while maintaining a high degree of programmability.
Asad A. Abidi - One of the best experts on this subject based on the ideXlab platform.
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The Path to the Software-Defined Radio Receiver
IEEE Journal of Solid-state Circuits, 2007Co-Authors: Asad A. AbidiAbstract:After being the subject of speculation for many years, a Software-Defined Radio receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that in mobile handsets, it is enough to receive one channel with any bandwidth, situated in any band. Thus, the front-end can be tuned electronically. Taking a cue from a digital front-end, the receiver's flexible analog baseband samples the channel of interest at zero IF, and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that of an RF prefilter, and a conversion rate that is low enough for A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A 90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels located anywhere from 800 MHz to 6 GHz
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Software-Defined Radio receiver: dream to reality
IEEE Communications Magazine, 2006Co-Authors: R. Bagheri, Ahmad Mirzaei, Mohammad E. Heidari, Saeed Chehrazi, Mohyee Mikhemar, Wai Tang, Asad A. AbidiAbstract:This article describes a fully integrated 90 nm CMOS Software-Defined Radio receiver operating in the 800 MHz to 5 GHz band. Unlike the classical SDR paradigm, which digitizes the whole spectrum uniformly, this receiver acts as a signal conditioner for the analog-to-digital converters, emphasizing only the wanted channel. Thus, the ADCs operate with modest resolution and sample rate, consuming low power. This approach makes portable SDR a reality
P B Kenington - One of the best experts on this subject based on the ideXlab platform.
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linearized transmitters an enabling technology for Software Defined Radio
IEEE Communications Magazine, 2002Co-Authors: P B KeningtonAbstract:Power amplifier and transmitter linearization techniques are now a mature technology, with feedforward systems installed in many US base station sites for both TDMA and CDMA systems. Similarly, transmitter linearization techniques, such as Cartesian loop and predistortion, have been employed in mobile and portable equipment, and these have enabled a number of systems (e.g., iDEN in the United States and TETRA in Europe) to be realizable from a power consumption, cost, and size perspective. Such techniques are essential in the realization of an efficient and cost-effective Software-Defined Radio system, whether deployed in a base station or a handset, and are thus a key enabling technology, without which SDR will not succeed. This article examines the current status of power amplifier and transmitter linearization technologies for mobile and base station equipment, and highlights some of the novel base station and network topologies now emerging based on these techniques. In many cases, these new topologies will revolutionize the way a cellular network is constructed and lead to very substantial cost reductions for a network operator.
